zach0zhang/Single_instruction_cycle_OpenMIPS external links

---

GitHub - View repository

GitHub.dev - Open in online code editor

Star history - Growth chart over time

deps.dev - Dependencies and security vulnerabilities

Gitingest - Export source code for LLM usage

Repomix - Export source code for LLM usage

uithub - Export source code for LLM usage

Close

zach0zhang/Single_instruction_cycle_OpenMIPS

Readme badge preview -

If you own this repo, copy the snippet below and add it to your README.md

---

Copy

[![RelatedRepos](https://img.shields.io/badge/related-repos-yellow)](https://relatedrepos.com/gh/zach0zhang/Single_instruction_cycle_OpenMIPS)

Close

zach0zhang / Single_instruction_cycle_OpenMIPSView on GitHubMore

• External links
• Readme badge

通过学习《自己动手写CPU》，将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS（五级流水线结构），简化成单指令周期实现的处理器

☆210Mar 2, 2022Updated 4 years ago

Alternatives and similar repositories for Single_instruction_cycle_OpenMIPS

Users that are interested in Single_instruction_cycle_OpenMIPS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.

• Z-Y00 / Examples-in-book-write-your-own-cpu

  View on GitHub
  《自己动手写CPU》一书附带的文件
  ☆87Mar 1, 2018Updated 8 years ago
• gundambox / DIY_OpenMIPS

  View on GitHub
  實作《自己動手寫CPU》書上的程式碼
  ☆69Sep 16, 2018Updated 7 years ago
• MashPlant / decaf-rs

  View on GitHub
  Framework of pa code for THU compiler principle course.
  ☆13Dec 18, 2019Updated 6 years ago
• Trinkle23897 / mips32-cpu

  View on GitHub
  奋战一学期，造台计算机（编译出的bit文件在release中，可以直接食用）
  ☆130Nov 13, 2019Updated 6 years ago
• muzilinxi90 / OpenMIPS

  View on GitHub
  OpenMIPS——《自己动手写CPU》处理器部分
  ☆22Mar 4, 2017Updated 9 years ago
• AI Agents on DigitalOcean Gradient AI Platform • Ad
  Build production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
• yufeiran / OpenMIPS

  View on GitHub
  实现一个基础但功能完善的计算机系统,根据《自己动手写ＣＰＵ》实现，开发板为Nexys4 DDR
  ☆34Mar 10, 2024Updated 2 years ago
• lvyufeng / step_into_mips

  View on GitHub
  一步一步写MIPS CPU
  ☆859Aug 4, 2021Updated 4 years ago
• Lyncien / RISC-V-32I

  View on GitHub
  体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器
  ☆87Nov 28, 2019Updated 6 years ago
• stceum / 8-bit-model-machine

  View on GitHub
  东北大学数字逻辑8位模型机课程设计
  ☆12Aug 2, 2020Updated 5 years ago
• freecores / mips_16

  View on GitHub
  Educational 16-bit MIPS Processor
  ☆18Feb 16, 2019Updated 7 years ago
• trivialmips / TrivialMIPS

  View on GitHub
  MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support
  ☆110Apr 29, 2019Updated 7 years ago
• 0xf3cd / CPU54-Pipeline

  View on GitHub
  CPU based on MIPS with 5-stage pipeline and cache, working with DDR2 memory and SD card.
  ☆32Sep 9, 2020Updated 5 years ago
• HaleLu / mips

  View on GitHub
  Mips处理器仿真设计
  ☆17Jun 22, 2016Updated 9 years ago
• Timothy-Liuxf / PipelineCPU

  View on GitHub
  清华大学电子工程系数字逻辑与处理器基础实验大作业——流水线 CPU
  ☆12Aug 8, 2021Updated 4 years ago
• 1-Click AI Models by DigitalOcean Gradient • Ad
  Deploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
• grantae / OpenMIPS

  View on GitHub
  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions,…
  ☆84Jun 5, 2019Updated 6 years ago
• SinnLiu / CPU_Design_MIPS

  View on GitHub
  《CPU设计实战》学习记录及代码
  ☆14Dec 30, 2023Updated 2 years ago
• jmahler / mips-cpu

  View on GitHub
  MIPS CPU implemented in Verilog
  ☆646Oct 3, 2017Updated 8 years ago
• Vulgarities / 31Ins-one-cycle-MipsCPU

  View on GitHub
  31条指令单周期MIPS cpu
  ☆15Jun 1, 2019Updated 6 years ago
• gyd111 / NAND-Flash-controller

  View on GitHub
  MT29F128G based NAND flash controller
  ☆10Jun 17, 2021Updated 4 years ago
• ztgao / ConvNN_FPGA_Accelerator

  View on GitHub
  ☆14Dec 17, 2015Updated 10 years ago
• RV-AT / PVS464

  View on GitHub
  ☆19Aug 10, 2020Updated 5 years ago
• decaf-lang / decaf-2019-project

  View on GitHub
  Decaf 实验综述
  ☆12Jan 7, 2020Updated 6 years ago
• rongcuid / riscv-megaproject

  View on GitHub
  A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earli…
  ☆29Nov 25, 2018Updated 7 years ago
• Deploy to Railway using AI coding agents - Free Credits Offer • Ad
  Use Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
• MUrielleMU / single-cycle-CPU

  View on GitHub
  单周期CPU设计与实现
  ☆14Dec 30, 2022Updated 3 years ago
• jhdjames37 / RISC-V-CPU-simple

  View on GitHub
  清华大学《计算机组成原理》大实验——五级流水线 RISC-V 处理器。「奋战三星期，造台计算机」
  ☆22Mar 11, 2023Updated 3 years ago
• LAOS-Y / AgriVision

  View on GitHub
  ☆18Jun 27, 2021Updated 4 years ago
• wmy367 / Radix-2-division

  View on GitHub
  unsigned Radix-2 SRT division,基2除法
  ☆16May 12, 2015Updated 10 years ago
• bluespec / Accel_AES

  View on GitHub
  ☆15Jun 1, 2019Updated 6 years ago
• freecores / ethernet_tri_mode

  View on GitHub
  10_100_1000 Mbps tri-mode ethernet MAC
  ☆10Jul 17, 2014Updated 11 years ago
• Starrynightzyq / soNN

  View on GitHub
  A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.
  ☆29Jul 14, 2021Updated 4 years ago
• daniellutscher / MixMatch-TransferLearning

  View on GitHub
  Combines the SSL Method MixMatch with a pre-trained model (EfficientNet) on a chest x-ray dataset.
  ☆11Jun 22, 2019Updated 6 years ago
• Bhagya-laxmi / nn_noxim

  View on GitHub
  Network on chip based neural network accelerator
  ☆11Mar 25, 2021Updated 5 years ago
• Serverless GPU API endpoints on Runpod - Get Bonus Credits • Ad
  Skip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
• light-ly / chisel-template

  View on GitHub
  自建 chisel 工程模板
  ☆14Jul 19, 2023Updated 2 years ago
• yasnakateb / PipelinedARM

  View on GitHub
  💎 A 32-bit ARM Processor Implementation in Verilog HDL
  ☆28Mar 21, 2022Updated 4 years ago
• Spiritator / FPGA_LeNet5_ws_8x8

  View on GitHub
  FPGA implement of 8x8 weight stationary systolic array DNN accelerator
  ☆18Feb 27, 2021Updated 5 years ago
• SI-RISCV / e200_opensource

  View on GitHub
  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
  ☆2,840Mar 24, 2021Updated 5 years ago
• Eslzzyl / riscv-pipeline-cpu

  View on GitHub
  合肥工业大学《系统硬件综合设计》五级流水线 RISC-V CPU
  ☆33Sep 24, 2023Updated 2 years ago
• Azalea8 / riscv_cpu

  View on GitHub
  riscv指令集，单周期以及五级流水线CPU
  ☆131Jan 6, 2025Updated last year
• eda-ricercatore / Lombardia-STIL

  View on GitHub
  A C++ -based STIL parser.
  ☆12Apr 29, 2021Updated 5 years ago