通过学习《自己动手写CPU》,将书中实现的兼容MIPS32指令集架构的处理器——OpenMIPS(五级流水线结构),简化成单指令周期实现的处理器
☆209Mar 2, 2022Updated 4 years ago
Alternatives and similar repositories for Single_instruction_cycle_OpenMIPS
Users that are interested in Single_instruction_cycle_OpenMIPS are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- 《自己动手写CPU》一书附带的文件☆87Mar 1, 2018Updated 8 years ago
- Framework of pa code for THU compiler principle course.☆13Dec 18, 2019Updated 6 years ago
- 奋战一学期,造台计算机(编译出的bit文件在release中,可以直接食用)☆130Nov 13, 2019Updated 6 years ago
- 实现一个基础但功能完善的计算机系统,根据《自己动手写CPU》实现,开发板为Nexys4 DDR☆34Mar 10, 2024Updated 2 years ago
- 2022WHU计算机系统综合设计 基于RISCV的五级流水线CPU Five stage CPU implement based on RISC-V☆12Oct 31, 2023Updated 2 years ago
- 一步一步写MIPS CPU☆854Aug 4, 2021Updated 4 years ago
- 体系结构课程实验:RISC-V 32I 流水线 CPU,实现37条指令,转发,冒险检测,Cache,分支预测器☆88Nov 28, 2019Updated 6 years ago
- MIPS32 CPU implemented in SystemVerilog, with superscalar and FPU support☆110Apr 29, 2019Updated 6 years ago
- 东北大学数字逻辑8位模型机课程设计☆12Aug 2, 2020Updated 5 years ago
- CPU based on MIPS with 5-stage pipeline and cache, working with DDR2 memory and SD card.☆32Sep 9, 2020Updated 5 years ago
- Mips处理器仿真设计☆17Jun 22, 2016Updated 9 years ago
- 清华大学电子工程系数字逻辑与处理器基础实验大作业——流水线 CPU☆12Aug 8, 2021Updated 4 years ago
- A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions,…☆83Jun 5, 2019Updated 6 years ago
- 《CPU设计实战》学习记录及代码☆14Dec 30, 2023Updated 2 years ago
- MIPS CPU implemented in Verilog☆645Oct 3, 2017Updated 8 years ago
- 合肥工业大学2020年《系统硬件综合设计》(《计算机组成原理》课程设计,CPU)的代码与报告;使用Verilog实现全冒险处理机制的MIPS五段流水CPU,支持MIPS-C3的50条指令。☆71Sep 25, 2020Updated 5 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- ☆19Aug 10, 2020Updated 5 years ago
- A series of (practise) projects of RISC-V cores. All cores will support at least the I instruction set. Expect bugs/limitations for earli…☆29Nov 25, 2018Updated 7 years ago
- 单周期CPU设计与实现☆14Dec 30, 2022Updated 3 years ago
- 清华大学《计算机组成原理》大实验——五级流水线 RISC-V 处理器。「奋战三星期,造台计算机」☆22Mar 11, 2023Updated 3 years ago
- ☆18Jun 27, 2021Updated 4 years ago
- unsigned Radix-2 SRT division,基2除法☆16May 12, 2015Updated 10 years ago
- A Reconfigurable Accelerator for Deep Convolutional Neural Networks Implemented by Chisel3.☆29Jul 14, 2021Updated 4 years ago
- 自建 chisel 工程模板☆14Jul 19, 2023Updated 2 years ago
- 操作系统课程实验设计☆12Mar 16, 2025Updated last year
- 💎 A 32-bit ARM Processor Implementation in Verilog HDL☆27Mar 21, 2022Updated 4 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,827Mar 24, 2021Updated 5 years ago
- FPGA implement of 8x8 weight stationary systolic array DNN accelerator☆17Feb 27, 2021Updated 5 years ago
- A C++ -based STIL parser.☆12Apr 29, 2021Updated 4 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Aug 28, 2016Updated 9 years ago
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Dec 14, 2020Updated 5 years ago
- OS教学实验:用Rust&C实现各种历史上的经典OS Kernels的实例☆47Apr 17, 2022Updated 3 years ago
- ☆18Jun 3, 2019Updated 6 years ago
- Verilog实现的简单五级流水线CPU,开发平台:Nexys3☆40Jul 9, 2015Updated 10 years ago
- 计算机组成原理课程32位监控程序☆50Jun 2, 2020Updated 5 years ago
- XCon: Learning with Experts for Fine-grained Category Discovery☆19Dec 19, 2022Updated 3 years ago
- Lua 5.3.0 源码阅读,阅读过程中加入注释方便理解☆17Oct 16, 2015Updated 10 years ago
- 和我一步一步实现一个最简单的、带数据前推及流水线暂停的32位静态五级流水MIPS☆84Nov 21, 2020Updated 5 years ago