KohakuBlueleaf / HakuTPULinks
An AI accelerator implementation with Xilinx FPGA
☆51Updated 7 months ago
Alternatives and similar repositories for HakuTPU
Users that are interested in HakuTPU are comparing it to the libraries listed below
Sorting:
- Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit☆159Updated last year
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆155Updated 2 years ago
- ☆99Updated last year
- Research and Materials on Hardware implementation of Transformer Model☆279Updated 6 months ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆127Updated 6 months ago
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆85Updated 7 months ago
- A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.☆428Updated 5 years ago
- ☆47Updated 4 months ago
- Small-scale Tensor Processing Unit built on an FPGA☆199Updated 6 years ago
- IC implementation of Systolic Array for TPU☆272Updated 10 months ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆139Updated 5 months ago
- ☆207Updated last year
- IC implementation of TPU☆129Updated 5 years ago
- GPGPU supporting RISCV-V, developed with verilog HDL☆108Updated 6 months ago
- Machine-Learning Accelerator System Exploration Tools☆173Updated 2 months ago
- CNN accelerator implemented with Spinal HDL☆152Updated last year
- Hardware accelerator for convolutional neural networks☆50Updated 3 years ago
- Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions☆198Updated 5 years ago
- Fully opensource spiking neural network accelerator☆154Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆185Updated last year
- NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.☆354Updated last year
- A Framework for Hardware-Aware LLM Exploration☆34Updated this week
- IEEE 754 floating point unit in Verilog☆145Updated 9 years ago
- Convolutional accelerator kernel, target ASIC & FPGA☆222Updated 2 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆104Updated 4 years ago
- An open source Verilog Based LeNet-1 Parallel CNNs Accelerator for FPGAs in Vivado 2017☆18Updated 6 years ago
- Systolic array based simple TPU for CNN on PYNQ-Z2☆35Updated 3 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆164Updated 5 years ago
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆53Updated last year
- An AXI4 crossbar implementation in SystemVerilog☆170Updated this week