Alternatives and similar repositories for HakuTPU

Users that are interested in HakuTPU are comparing it to the libraries listed below

• rejunity / tiny-asic-1_58bit-matrix-mul
  Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
  ☆169Updated last year
• HLSTransform / submission
  ☆111Updated last year
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆137Updated 9 months ago
• DeepWok / mase
  Machine-Learning Accelerator System Exploration Tools
  ☆183Updated 3 weeks ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆204Updated 5 years ago
• aliemo / transfomers-silicon-research
  Research and Materials on Hardware implementation of Transformer Model
  ☆287Updated 8 months ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆106Updated 10 months ago
• 8krisv / CNN-ACCELERATOR
  Hardware accelerator for convolutional neural networks
  ☆59Updated 3 years ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆160Updated 2 years ago
• pulp-platform / ITA
  ☆57Updated 7 months ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆155Updated 8 months ago
• abdelazeem201 / Systolic-array-implementation-in-RTL-for-TPU
  IC implementation of Systolic Array for TPU
  ☆299Updated last year
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆97Updated 3 weeks ago
• KULeuven-MICAS / zigzag
  HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
  ☆165Updated 3 weeks ago
• arasi15 / CNN-Accelerator-Implementation-based-on-Eyerissv2
  ☆120Updated 5 years ago
• cameronshinn / tiny-tpu
  Small-scale Tensor Processing Unit built on an FPGA
  ☆207Updated 6 years ago
• BoooC / CNN-Accelerator-Based-on-Eyeriss-v2
  A Flexible and Energy Efficient Accelerator For Sparse Convolution Neural Network
  ☆118Updated 4 months ago
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆135Updated 5 years ago
• yuyuranium / FPGA-Project-2022-simple-tpu
  Systolic array based simple TPU for CNN on PYNQ-Z2
  ☆37Updated 3 years ago
• karthisugumar / CSE240D-Hierarchical_Mesh_NoC-Eyeriss_v2
  A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…
  ☆176Updated 5 years ago
• ReaLLMASIC / ReaLLM-Forge
  A Framework for Hardware-Aware LLM Exploration
  ☆35Updated this week
• intel / fpga-npu
  ☆223Updated last year
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆107Updated 5 years ago
• lirui-shanghaitech / CNN-Accelerator-VLSI
  Convolutional accelerator kernel, target ASIC & FPGA
  ☆234Updated 2 years ago
• albertomarchisio / SwiftTron
  ☆46Updated 2 years ago
• Dazhuzhu-github / systolic-array
  verilog实现TPU中的脉动阵列计算卷积的module
  ☆138Updated 6 months ago
• sfmth / OpenSpike
  Fully opensource spiking neural network accelerator
  ☆162Updated 2 years ago
• debtanu09 / systolic_array_matrix_multiplier
  This is a verilog implementation of 4x4 systolic array multiplier
  ☆70Updated 5 years ago
• Buck008 / Transformer-Accelerator-Based-on-FPGA
  You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…
  ☆209Updated last year
• 0x5b25 / CNN_Core
  A CNN accelerator design inspired by MIT Eyeriss project
  ☆20Updated 4 years ago