rejunity / tiny-asic-1_58bit-matrix-mulLinks
Tiny ASIC implementation for "The Era of 1-bit LLMs All Large Language Models are in 1.58 Bits" matrix multiplication unit
☆155Updated last year
Alternatives and similar repositories for tiny-asic-1_58bit-matrix-mul
Users that are interested in tiny-asic-1_58bit-matrix-mul are comparing it to the libraries listed below
Sorting:
- ☆94Updated last year
- Machine-Learning Accelerator System Exploration Tools☆168Updated 3 weeks ago
- An AI accelerator implementation with Xilinx FPGA☆46Updated 4 months ago
- ShiftAddLLM: Accelerating Pretrained LLMs via Post-Training Multiplication-Less Reparameterization☆109Updated 8 months ago
- The Riallto Open Source Project from AMD☆81Updated 2 months ago
- A high-efficiency system-on-chip for floating-point compute workloads.☆36Updated 5 months ago
- ☆24Updated last year
- A survey on Hardware Accelerated LLMs☆55Updated 5 months ago
- A new LLM solution for RTL code generation, achieving state-of-the-art performance in non-commercial solutions and outperforming GPT-3.5.☆203Updated 4 months ago
- Verilog evaluation benchmark for large language model☆279Updated 4 months ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆81Updated last month
- Ocelot: The Berkeley Out-of-Order Machine With V-EXT support☆169Updated 5 months ago
- 1.58-bit LLaMa model☆81Updated last year
- An efficent implementation of the method proposed in "The Era of 1-bit LLMs"☆154Updated 8 months ago
- ☆43Updated 3 weeks ago
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆37Updated 2 months ago
- Run 64-bit Linux on LiteX + RocketChip☆199Updated 10 months ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆152Updated 2 years ago
- Experimental BitNet Implementation☆67Updated this week
- PDPU: An Open-Source Posit Dot-Product Unit for Deep Learning Applications☆41Updated 2 years ago
- Torch2Chip (MLSys, 2024)☆52Updated 2 months ago
- ☆47Updated 2 months ago
- ☆28Updated 3 months ago
- Self checking RISC-V directed tests☆108Updated 3 weeks ago
- ☆137Updated this week
- ☆21Updated this week
- Research and Materials on Hardware implementation of Transformer Model☆265Updated 3 months ago
- Open-source RTL logic simulator with CUDA acceleration☆86Updated this week
- [BRH YT CHANNEL] This repo contains all the code and ressources you need for the Zynq tutorials, ready to copy and paste.☆56Updated last month
- An energy-efficient RISC-V floating-point compute cluster.☆88Updated last week