Alternatives and similar repositories for submission

Users that are interested in submission are comparing it to the libraries listed below

• DeepWok / mase
  Machine-Learning Accelerator System Exploration Tools
  ☆166Updated last week
• arc-research-lab / CHARM
  CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture
  ☆143Updated this week
• pulp-platform / ITA
  ☆47Updated last month
• KastnerRG / cgra4ml
  An Open Workflow to Build Custom SoCs and run Deep Models at the Edge
  ☆79Updated 2 weeks ago
• SamsungLabs / Butterfly_Acc
  The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …
  ☆135Updated 2 years ago
• UCLA-VAST / AutoSA
  AutoSA: Polyhedral-Based Systolic Array Compiler
  ☆221Updated 2 years ago
• makslevental / openhls
  PyTorch model to RTL flow for low latency inference
  ☆126Updated last year
• kachris / survey_HA_LLM
  A survey on Hardware Accelerated LLMs
  ☆52Updated 4 months ago
• hguq / HG-PIPE
  FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.
  ☆56Updated 4 months ago
• ucb-bar / onnxruntime-riscv
  Fork of upstream onnxruntime focused on supporting risc-v accelerators
  ☆87Updated 2 years ago
• embedeep / FREE-TPU-V3plus-for-FPGA
  FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference
  ☆146Updated last year
• actlab-genesys / GeneSys
  An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.
  ☆53Updated 2 months ago
• aliemo / transfomers-silicon-research
  Research and Materials on Hardware implementation of Transformer Model
  ☆264Updated 3 months ago
• jha-lab / acceltran
  [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers
  ☆43Updated last year
• cornell-zhang / HiSparse
  High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS
  ☆91Updated 8 months ago
• KULeuven-MICAS / stream
  Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.
  ☆53Updated last month
• linghaosong / Sextans
  An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).
  ☆79Updated 10 months ago
• gnodipac886 / ViT-FPGA-TPU
  FPGA based Vision Transformer accelerator (Harvard CS205)
  ☆119Updated 3 months ago
• BUAA-CI-LAB / Literatures-on-SRAM-based-CIM
  A reading list for SRAM-based Compute-In-Memory (CIM) research.
  ☆65Updated 3 months ago
• thousrm / universal_NPU-CNN_accelerator
  hardware design of universal NPU(CNN accelerator) for various convolution neural network
  ☆125Updated 3 months ago
• tancheng / CGRA-Flow
  CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.
  ☆129Updated last week
• cornell-zhang / allo
  Allo: A Programming Model for Composable Accelerator Design
  ☆235Updated last week
• FlightLLM / flightllm_test_demo
  ☆23Updated last year
• arc-research-lab / SSR
  SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)
  ☆32Updated this week
• leo47007 / TPU-Tensor-Processing-Unit
  IC implementation of TPU
  ☆125Updated 5 years ago
• SingularityKChen / dl_accelerator
  Deep Learning Accelerator Based on Eyeriss V2 Architecture with custom RISC-V extended instructions
  ☆192Updated 4 years ago
• KULeuven-MICAS / zigzag
  HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators
  ☆150Updated 2 months ago
• mit-han-lab / spatten
  [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning
  ☆93Updated 9 months ago
• sharc-lab / FlowGNN
  A dataflow architecture for universal graph neural network inference via multi-queue streaming.
  ☆73Updated 2 years ago
• PSAL-POSTECH / ONNXim
  ONNXim is a fast cycle-level simulator that can model multi-core NPUs for DNN inference
  ☆118Updated 3 months ago