HLSTransform / submission
☆89Updated last year
Alternatives and similar repositories for submission
Users that are interested in submission are comparing it to the libraries listed below
Sorting:
- Machine-Learning Accelerator System Exploration Tools☆161Updated 2 weeks ago
- CHARM: Composing Heterogeneous Accelerators on Heterogeneous SoC Architecture☆142Updated this week
- Research and Materials on Hardware implementation of Transformer Model☆258Updated 2 months ago
- A survey on Hardware Accelerated LLMs☆51Updated 4 months ago
- The codes and artifacts associated with our MICRO'22 paper titled: "Adaptable Butterfly Accelerator for Attention-based NNs via Hardware …☆131Updated last year
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆77Updated this week
- FPGA-based hardware accelerator for Vision Transformer (ViT), with Hybrid-Grained Pipeline.☆53Updated 3 months ago
- ☆42Updated 3 weeks ago
- PyTorch model to RTL flow for low latency inference☆126Updated last year
- High-Performance Sparse Linear Algebra on HBM-Equipped FPGAs Using HLS☆90Updated 7 months ago
- hardware design of universal NPU(CNN accelerator) for various convolution neural network☆119Updated 2 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆79Updated 9 months ago
- An FPGA Accelerator for Transformer Inference☆81Updated 3 years ago
- FPGA based Vision Transformer accelerator (Harvard CS205)☆118Updated 3 months ago
- Allo: A Programming Model for Composable Accelerator Design☆228Updated last week
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆51Updated 2 months ago
- FREE TPU V3plus for FPGA is the free version of a commercial AI processor (EEP-TPU) for Deep Learning EDGE Inference☆145Updated last year
- HW Architecture-Mapping Design Space Exploration Framework for Deep Learning Accelerators☆146Updated last month
- [TCAD'23] AccelTran: A Sparsity-Aware Accelerator for Transformers☆41Updated last year
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆30Updated last month
- AutoSA: Polyhedral-Based Systolic Array Compiler☆218Updated 2 years ago
- SSR: Spatial Sequential Hybrid Architecture for Latency Throughput Tradeoff in Transformer Acceleration (Full Paper Accepted in FPGA'24)☆31Updated this week
- ☆43Updated 2 years ago
- IC implementation of Systolic Array for TPU☆235Updated 6 months ago
- Verilog implementation of Softmax function☆65Updated 2 years ago
- You can run it on pynq z1. The repository contains the relevant Verilog code, Vivado configuration and C code for sdk testing. The size o…☆172Updated last year
- [HPCA'21] SpAtten: Efficient Sparse Attention Architecture with Cascade Token and Head Pruning☆86Updated 8 months ago
- CGRA-Flow is an integrated framework for CGRA compilation, exploration, synthesis, and development.☆127Updated last week
- ☆22Updated last year
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆52Updated last year