IAMAl / ML-Hardware-Collections
News and Paper Collections for Machine Learning Hardware
☆20Updated 4 months ago
Related projects: ⓘ
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆48Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆42Updated 2 years ago
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆56Updated 2 years ago
- ☆47Updated 8 months ago
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆23Updated 4 years ago
- A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.☆60Updated 2 years ago
- Adaptive floating-point based numerical format for resilient deep learning☆14Updated 2 years ago
- ☆20Updated last year
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆44Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆41Updated 3 months ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆62Updated last month
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆62Updated 5 years ago
- ☆65Updated last year
- Dynamically Reconfigurable Architecture Template and Cycle-level Microarchitecture Simulator for Dataflow AcCelerators☆26Updated last year
- ☆32Updated 5 years ago
- Fork of seldridge/rocket-rocc-examples with tests for a systolic array based matmul accelerator☆53Updated 2 weeks ago
- Docker container with tools for the Timeloop/Accelergy tutorial☆23Updated 5 months ago
- [DAC 2020] Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency☆32Updated 3 years ago
- ☆53Updated 4 years ago
- Eyeriss chip simulator☆31Updated 4 years ago
- ☆15Updated 2 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆34Updated this week
- ☆31Updated 3 years ago
- CGRA framework with vectorization support.☆18Updated 5 months ago
- ☆28Updated 2 weeks ago
- ☆38Updated last week
- SAMO: Streaming Architecture Mapping Optimisation☆31Updated 11 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆20Updated 5 months ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆58Updated 9 months ago
- ☆13Updated 4 years ago