IAMAl / ML-Hardware-CollectionsLinks
News and Paper Collections for Machine Learning Hardware
☆22Updated last year
Alternatives and similar repositories for ML-Hardware-Collections
Users that are interested in ML-Hardware-Collections are comparing it to the libraries listed below
Sorting:
- Fork of upstream onnxruntime focused on supporting risc-v accelerators☆88Updated 2 years ago
- FlexASR: A Reconfigurable Hardware Accelerator for Attention-based Seq-to-Seq Networks☆46Updated 5 months ago
- A DSL for Systolic Arrays☆80Updated 6 years ago
- PyTorch model to RTL flow for low latency inference☆130Updated last year
- NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions☆37Updated 4 months ago
- ☆36Updated 4 months ago
- Train and deploy LUT-based neural networks on FPGAs☆97Updated last year
- ☆72Updated 2 years ago
- A Spatial Accelerator Generation Framework for Tensor Algebra.☆58Updated 3 years ago
- ☆71Updated this week
- ☆23Updated 2 years ago
- Linux docker for the DNN accelerator exploration infrastructure composed of Accelergy and Timeloop☆56Updated 3 months ago
- ☆58Updated 5 years ago
- Multi-core HW accelerator mapping optimization framework for layer-fused ML workloads.☆57Updated last month
- MAERI: A DNN accelerator with reconfigurable interconnects to support flexible dataflow (http://synergy.ece.gatech.edu/tools/maeri/)☆64Updated 3 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago
- SAMO: Streaming Architecture Mapping Optimisation☆34Updated last year
- ☆47Updated 3 months ago
- ☆59Updated this week
- Provides the hardware code for the paper "EBPC: Extended Bit-Plane Compression for Deep Neural Network Inference and Training Accelerator…☆24Updated 5 years ago
- An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM).☆81Updated last year
- Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.☆76Updated 6 years ago
- dMazeRunner: Dataflow acceleration optimization infrastructure for coarse-grained programmable accelerators☆46Updated 3 years ago
- PiDRAM is the first flexible end-to-end framework that enables system integration studies and evaluation of real Processing-using-Memory …☆68Updated last year
- Algorithmic C Machine Learning Library☆26Updated 7 months ago
- ☆37Updated 3 years ago
- An LLVM pass that can generate CDFG and map the target loops onto a parameterizable CGRA.☆74Updated last week
- An MLIR dialect to enable the efficient acceleration of ML model on CGRAs.☆60Updated 9 months ago
- An open-source parameterizable NPU generator with full-stack multi-target compilation stack for intelligent workloads.☆60Updated 4 months ago
- A Reconfigurable Accelerator with Data Reordering Support for Low-Cost On-Chip Dataflow Switching☆56Updated 4 months ago