Alternatives and similar repositories for bilinear:

Users that are interested in bilinear are comparing it to the libraries listed below

• xiesicong / fpga_sobel_ov5640_hdmi
  fpga跑sobel识别算法
  ☆29Updated 4 years ago
• Nitcloud / Image_sim
  基于FPGA的图像处理模块（出自于crazybingo）（将部分IP换为纯Verilog用于跨平台移植）
  ☆46Updated 4 years ago
• Aperture-Electronic / SystemVerilog-Bitmap-Library-AXI-Image-VIP
  Bitmap Processing Library & AXI-Stream Video Image VIP
  ☆30Updated 2 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆97Updated 5 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆54Updated 8 years ago
• VenciFreeman / FFT_ChipDesign
  A 16-point radix-4 FFT chip, including Verilog codes, netlists and layout. Group project.
  ☆60Updated 7 months ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆63Updated 5 years ago
• bird1and1fish / Frame_Difference
  FPGA实现动态图像识别
  ☆19Updated 4 years ago
• Starrynightzyq / ZYNQ-PYNQ-Z2-Gobang
  2018第二届全国大学生FPGA创新设计邀请赛的作品
  ☆59Updated 6 years ago
• CodeNameGrapefruit / SoC_CNN
  Convolutional Neural Network Implemented in Verilog for System on Chip
  ☆27Updated 5 years ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆41Updated 4 years ago
• 2cc2ic / DMA-S2MM-and-MM2S
  Build an open source, extremely simple DMA.
  ☆21Updated 6 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆33Updated 4 years ago
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆36Updated 3 years ago
• iharbour-heyaonan / FPGA_image_process
  FPGA实现简单的图像处理算法
  ☆41Updated 2 years ago
• Zero0Hero / yolo_e203_fpga
  Nuclei E203 with yolo accelerator based on xc7k325
  ☆13Updated 8 months ago
• markos-stefanidis / FPGA-Based-HDR-algorithm
  Hardware implementation of HDR image producing algorithm
  ☆16Updated 2 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆36Updated 8 years ago
• freecores / dma_ahb
  AHB DMA 32 / 64 bits
  ☆54Updated 10 years ago
• eda-lab / CNNAF-CNN-Accelerator_init
  CNN-Accelerator based on FPGA developed by verilog HDL.
  ☆47Updated 4 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆52Updated 3 years ago
• mayshin10 / CNN-Accelerator
  Designing CNN accelerator using a Xilinx FPGA board and comparing performance with CPU.
  ☆22Updated 4 years ago
• ryaanluke / DNN-Hardware-Accelerator
  SystemVerilog files for lab project on a DNN hardware accelerator
  ☆16Updated 3 years ago
• GuoningHuang / FPGA-CNN-accelerator-based-on-systolic-array
  2023集创赛国二。基于脉动阵列写的一个简单的卷积层加速器，支持yolov3-tiny的第一层卷积层计算，可根据FPGA端DSP资源灵活调整脉动阵列的结构以实现不同的计算效率。
  ☆160Updated 5 months ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆39Updated 3 years ago
• lucky-wfw / IC_System_Design
  Use Verilog to complete the design of various digital circuits, including common interfaces, such as UART, Bluetooth, IIC, AMBA, etc. It …
  ☆27Updated 4 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆111Updated 10 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• zhangzek / 3x3_matrix_Systolic_Array_multiplier
  3×3脉动阵列乘法器
  ☆44Updated 5 years ago
• Thes0me / pango_video_local_dimming
  2022年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛紫光同创赛道视频色度亮度提取赛题设计源文件
  ☆32Updated 2 years ago