Essenceia / Nasdaq-HFT-FPGA
RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.
☆37Updated last year
Alternatives and similar repositories for Nasdaq-HFT-FPGA:
Users that are interested in Nasdaq-HFT-FPGA are comparing it to the libraries listed below
- High Frequency Trading using Vivado HLS☆136Updated 7 years ago
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆35Updated last year
- The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, orde…☆92Updated 11 months ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆14Updated last year
- Use NetFPGA SUME to implement HFT Machine based on TWSE Stock Server☆27Updated 6 years ago
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆26Updated last year
- 100 Gbps TCP/IP stack for Vitis shells☆203Updated 11 months ago
- Ethernet 10GE MAC☆45Updated 10 years ago
- TCP/IP and UDP/IP protocol stack off-loading☆16Updated 4 years ago
- Source files for Getting to Know Vivado course☆19Updated 4 years ago
- An open-source Ternary Content Addressable Memory (TCAM) compiler.☆27Updated 8 months ago
- 10G Low Latency Ethernet☆48Updated last year
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆124Updated 3 years ago
- Ethernet switch implementation written in Verilog☆45Updated last year
- Ethernet interface modules for Cocotb☆60Updated last year
- VNx: Vitis Network Examples☆145Updated 7 months ago
- Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…☆17Updated 5 years ago
- Alveo Versal Example Design☆36Updated last month
- An open source, parameterized SystemVerilog digital hardware IP library☆26Updated 10 months ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆23Updated 4 months ago
- This project aims at implementing an hardware accelerator peripheral for SHA256 hashing algorithm with AXI4 interfacing with PicoRV32 CPU…☆21Updated 3 years ago
- Library defining all Ethernet packets in SystemVerilog and in SystemC☆36Updated 8 years ago
- Single-source shortest paths accelerated with AWS F1 FPGA☆14Updated 6 years ago
- General Purpose AXI Direct Memory Access☆49Updated 10 months ago
- Introductory course into static timing analysis (STA).☆90Updated 4 months ago
- Write a CPU from scratch! (5-stage pipeline & 2-way-cache)☆12Updated 5 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆64Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆69Updated last week
- RoCEv2 hardware implementation in Bluespec SystemVerilog☆23Updated 6 months ago
- Simple hash table on Verilog (SystemVerilog)☆48Updated 8 years ago