Alternatives and similar repositories for Nasdaq-HFT-FPGA

Users that are interested in Nasdaq-HFT-FPGA are comparing it to the libraries listed below

• mustafabbas / ECE1373_2016_hft_on_fpga
  High Frequency Trading using Vivado HLS
  ☆154Updated 8 years ago
• Essenceia / low-latency-ethernet
  RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
  ☆44Updated last year
• muditbhargava66 / High-Frequency-Trading-FPGA-System
  The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, orde…
  ☆139Updated last year
• PremRL / fix-tcpip-project
  Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.
  ☆18Updated last year
• nckubugman / NetFPGA-SUME-High-Frequency-Trading-Machine
  Use NetFPGA SUME to implement HFT Machine based on TWSE Stock Server
  ☆30Updated 6 years ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆30Updated last year
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆132Updated 4 years ago
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆219Updated last year
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆45Updated 11 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆113Updated 3 years ago
• ATaylorCEngFIET / Getting-to-Know-Vivado
  Source files for Getting to Know Vivado course
  ☆19Updated 5 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆26Updated 9 months ago
• tharinduSamare / Multicore_processor_verilog_design
  This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.
  ☆11Updated 3 years ago
• akzare / HardORB
  TCP/IP and UDP/IP protocol stack off-loading
  ☆19Updated 5 years ago
• JeffDeCola / my-verilog-examples
  A place to keep my synthesizable verilog examples.
  ☆44Updated 5 months ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆179Updated last month
• Xilinx / HLS_packet_processing
  ☆47Updated 5 years ago
• alexforencich / dma-bench
  ☆28Updated 3 years ago
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆61Updated 2 years ago
• vlsiexcellence / Digital-ASIC-Design-Projects-
  Verilog Design, Simulation & Synthesis of Digital ASIC Projects
  ☆16Updated 2 years ago
• Xilinx / AVED
  Alveo Versal Example Design
  ☆46Updated last week
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆50Updated 9 years ago
• xver / Shunt
  SystemVerilog DPI "TCP/IP Shunt" (System Verilog/SystemC/Python TCP/IP socket library)
  ☆49Updated 2 months ago
• woshiyyya / RISCV-CPU
  Write a CPU from scratch! (5-stage pipeline & 2-way-cache)
  ☆20Updated 6 years ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆79Updated 7 years ago
• adki / DPI_Tutorial
  SystemVerilog Direct Programming Interface (DPI) Tutorial
  ☆70Updated 4 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆59Updated last year
• datenlord / blue-rdma
  RoCEv2 hardware implementation in Bluespec SystemVerilog
  ☆30Updated last year
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆67Updated 7 months ago
• FPGA-Networking / Low-Cost-and-Programmable-CRC
  Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"
  ☆43Updated 4 years ago