Alternatives and similar repositories for Nasdaq-HFT-FPGA

Users that are interested in Nasdaq-HFT-FPGA are comparing it to the libraries listed below

• mustafabbas / ECE1373_2016_hft_on_fpga
  High Frequency Trading using Vivado HLS
  ☆147Updated 8 years ago
• muditbhargava66 / High-Frequency-Trading-FPGA-System
  The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, orde…
  ☆107Updated last year
• Essenceia / low-latency-ethernet
  RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
  ☆41Updated last year
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆211Updated last year
• nckubugman / NetFPGA-SUME-High-Frequency-Trading-Machine
  Use NetFPGA SUME to implement HFT Machine based on TWSE Stock Server
  ☆28Updated 6 years ago
• PremRL / fix-tcpip-project
  Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.
  ☆16Updated last year
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆127Updated 3 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆107Updated 3 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆45Updated 11 years ago
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆49Updated 9 years ago
• ATaylorCEngFIET / Getting-to-Know-Vivado
  Source files for Getting to Know Vivado course
  ☆19Updated 4 years ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆28Updated last year
• Xilinx / HLS_packet_processing
  ☆47Updated 5 years ago
• shuckc / verilog-utils
  native Verilog pcap, littletoe, bcd, xml and hash modules, with Icarus testbenches
  ☆44Updated 10 years ago
• Xilinx / xup_vitis_network_example
  VNx: Vitis Network Examples
  ☆150Updated 11 months ago
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆56Updated 2 years ago
• sach / System-Verilog-Packet-Library
  System-Veilog Packet Library to configure, randomize, pack/unpack, copy, compare/display different headers
  ☆76Updated 6 years ago
• alexforencich / cocotbext-pcie
  PCI express simulation framework for Cocotb
  ☆168Updated 2 months ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆270Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆94Updated last week
• tharinduSamare / Multicore_processor_verilog_design
  This is a multi-core processor specially designed for matrix multiplication using Verilog HDL.
  ☆11Updated 3 years ago
• learn-cocotb / tutorial
  Complete tutorial code.
  ☆21Updated last year
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆67Updated last year
• akzare / HardORB
  TCP/IP and UDP/IP protocol stack off-loading
  ☆18Updated 4 years ago
• woshiyyya / RISCV-CPU
  Write a CPU from scratch! (5-stage pipeline & 2-way-cache)
  ☆18Updated 6 years ago
• hlslibs / ac_ml
  Algorithmic C Machine Learning Library
  ☆25Updated 7 months ago
• accellera-official / uvm-core
  ☆87Updated 10 months ago
• hypernyan / eth_vlg
  ☆70Updated 3 years ago
• SRA-VJTI / synapse32
  An inhouse RISC-V 32-bits CPU
  ☆14Updated 3 weeks ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆161Updated last month