Essenceia / Nasdaq-HFT-FPGA

Related projects ⓘ

Alternatives and complementary repositories for Nasdaq-HFT-FPGA

• Essenceia / low-latency-ethernet
  RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.
  ☆23Updated 10 months ago
• mustafabbas / ECE1373_2016_hft_on_fpga
  High Frequency Trading using Vivado HLS
  ☆120Updated 7 years ago
• muditbhargava66 / High-Frequency-Trading-FPGA-System
  The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, orde…
  ☆60Updated 6 months ago
• Essenceia / ethernet-physical-layer
  RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.
  ☆19Updated 10 months ago
• nckubugman / NetFPGA-SUME-High-Frequency-Trading-Machine
  Use NetFPGA SUME to implement HFT Machine based on TWSE Stock Server
  ☆26Updated 6 years ago
• hpcn-uam / efficient_checksum-offload-engine
  Checksum plays a key role in the TCP/IP headers. In this repo you'll find a efficient FPGA-based solution for a 512-bit AXI4-Stream inter…
  ☆16Updated 5 years ago
• Xilinx / HLS_packet_processing
  ☆45Updated 4 years ago
• ATaylorCEngFIET / Getting-to-Know-Vivado
  Source files for Getting to Know Vivado course
  ☆19Updated 4 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆44Updated 10 years ago
• ttchisholm / 10g-low-latency-ethernet
  10G Low Latency Ethernet
  ☆41Updated last year
• fpgasystems / Vitis_with_100Gbps_TCP-IP
  100 Gbps TCP/IP stack for Vitis shells
  ☆184Updated 6 months ago
• PremRL / fix-tcpip-project
  Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.
  ☆11Updated 11 months ago
• johan92 / fpga-hash-table
  Simple hash table on Verilog (SystemVerilog)
  ☆47Updated 8 years ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆59Updated this week
• corundum / ethernet-switch
  Ethernet switch implementation written in Verilog
  ☆40Updated last year
• JakeMercer / mac
  An Ethernet MAC conforming to IEEE 802.3
  ☆16Updated 7 years ago
• hpcn-uam / Limago
  Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack
  ☆122Updated 3 years ago
• avidan-efody / wave_searcher
  Implementation of post-process coverage, and batch waveform search
  ☆15Updated 3 years ago
• bensampson5 / libsv
  An open source, parameterized SystemVerilog digital hardware IP library
  ☆23Updated 5 months ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆102Updated 2 years ago
• varunnagpaal / Digital-Hardware-Modelling
  Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)
  ☆59Updated 3 years ago
• hpcn-uam / 100G-fpga-network-stack-core
  This repo contains the Limago code
  ☆78Updated 2 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆47Updated 2 years ago
• JeffDeCola / my-verilog-examples
  A place to keep my synthesizable verilog examples.
  ☆30Updated last year
• thinkoco / systemverilog-python
  Systemverilog DPI-C call Python function
  ☆19Updated 3 years ago
• Xilinx / open-nic-driver
  AMD OpenNIC driver includes the Linux kernel driver
  ☆55Updated 8 months ago
• datenlord / blue-rdma
  RoCEv2 hardware implementation in Bluespec SystemVerilog
  ☆19Updated 2 months ago
• Xilinx / open-nic-shell
  AMD OpenNIC Shell includes the HDL source files
  ☆99Updated 5 months ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆56Updated last year
• alexforencich / dma-bench
  ☆25Updated 2 years ago