muditbhargava66 / High-Frequency-Trading-FPGA-SystemLinks
The High-Frequency Trading FPGA System is an ultra-low latency platform for electronic trading on FPGAs. It features a TCP/IP stack, order matching engine, custom IP core, and risk management module for accelerated and reliable trade execution.
☆135Updated last year
Alternatives and similar repositories for High-Frequency-Trading-FPGA-System
Users that are interested in High-Frequency-Trading-FPGA-System are comparing it to the libraries listed below
Sorting:
- High Frequency Trading using Vivado HLS☆154Updated 8 years ago
- RTL design for a nasdaq compatible high frequency trading low level. Supports itch on moldudp64.☆54Updated last year
- RTL implementation of the low latency ethernet modules for the NASDAQ HFT FPGA project.☆44Updated last year
- SystemVerilog Tutorial☆170Updated 4 months ago
- HackerRank test solutions for FPGA engineer interview at Optiver☆10Updated 5 years ago
- This is a passion project where I aim to explore the RTL design topics of my interest.☆14Updated 3 months ago
- Hardware design project of the FIX and TCP/IP offload engines on FPGA, containing HDL codes and Python codes for testing.☆18Updated last year
- VSDSquadron Research Internship 2024 program where we learn about RISC-V processor and VLSI Design using various open source tools.☆30Updated last month
- Verilog HDL files☆152Updated last year
- AXI, AXI stream, Ethernet, and PCIe components in System Verilog☆378Updated last week
- ☆224Updated last month
- 10G Low Latency Ethernet☆59Updated 2 years ago
- Ethernet 10GE MAC☆45Updated 11 years ago
- AXI interface modules for Cocotb☆283Updated last week
- A collection of reusable, high-quality, peer-reviewed VHDL building blocks.☆180Updated last week
- This repo provide an index of VLSI content creators and their materials☆157Updated last year
- Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL☆115Updated 3 years ago
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆152Updated last year
- Limago: an FPGA-based Open-source 100 GbE TCP/IP Stack☆130Updated 4 years ago
- Implementation of RISC-V RV32I☆22Updated 3 years ago
- ☆115Updated last year
- ☆165Updated 3 years ago
- 100 Days of RTL☆392Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆94Updated 2 years ago
- An inhouse RISC-V 32-bits CPU☆16Updated 2 months ago
- Verilog digital signal processing components☆155Updated 2 years ago
- My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu☆144Updated 4 years ago
- 100 Gbps TCP/IP stack for Vitis shells☆218Updated last year
- RTL implementation of the ethernet physical layer PCS for 10GBASE-R and 40GBASE-R.☆30Updated last year
- Welcome to the 108 RTL Projects repository! This collection aims to provide a comprehensive set of RTL design projects ranging from simpl…☆23Updated 8 months ago