Alternatives and similar repositories for ECG-feature-extraction-using-DWT

Users that are interested in ECG-feature-extraction-using-DWT are comparing it to the libraries listed below

• tom-urkin / AMBA
  AHB-lite, AHB-APB bridge and extended APB side architecture in SystemVerilog
  ☆14Updated last year
• visky2096 / AHB-to-I2C
  Attempt to setup a bridge between AHB and I2C by constructing dedicated modules of AHB master , AHB slave , APB master , APB slave, I2C m…
  ☆22Updated 6 years ago
• MaharshSuryawala / Image-Compression
  Modified the conventional JPEG compression algorithm with Lloyd-Max Quantizer. Implemented in MATLAB and tested on Xilinx Artix-7 FPGA.
  ☆16Updated 4 years ago
• CountingLogic / ECG-Verilog-FPGA
  An accurate Electro Cardio Graph system, with peak detection and counting mechanism programmed in Verilog.
  ☆13Updated 6 years ago
• AmrElsersy / DMA
  DMA Hardware Description with Verilog
  ☆14Updated 5 years ago
• JoseIuri / axi4lite2uart
  This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.
  ☆20Updated 6 years ago
• kdurant / axi-ddr3
  学习AXI接口，以及xilinx DDR3 IP使用
  ☆37Updated 8 years ago
• funannoka / SoC-Design-DDR3-Controller
  DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog
  ☆31Updated 6 years ago
• AugustinJose1221 / FFTx32
  A 32 point radix-2 FFT module written in Verilog
  ☆23Updated 4 years ago
• VGuoGavin / Hand-Writing-Digital-Recognization-Based-on-FPGA
  Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The…
  ☆12Updated 2 years ago
• srohit0 / CORDIC
  CORDIC VLSI-IP for deep learning activation functions
  ☆15Updated 5 years ago
• DeamonYang / FPGA_FFT
  基于FPGA的FFT
  ☆18Updated 6 years ago
• bselimoglu / SoC-ZedBoard-Zynq-7000-Labs
  Hardware and Software Co-design implementations
  ☆14Updated 5 years ago
• fighter212 / ahb2apb
  this is an AHB to APB bridge with Synopsys VIP based test enviroment. RTL can be found from UVM website.
  ☆17Updated 10 years ago
• zhangkunming0216 / FIFO_-asynchronous
  异步FIFO的内部实现
  ☆24Updated 6 years ago
• efabless / raptor_soc_template
  Raptor is an SoC Design Template based on Arm Cortex M0 or M3 core.
  ☆21Updated 5 years ago
• open-dv / dma_axi
  ☆16Updated 6 years ago
• fengyulin1996 / Verilog-DSP
  FIR，FFT based on Verilog
  ☆13Updated 7 years ago
• letitbe0201 / AXI-DMA-master-verification
  ☆25Updated 4 years ago
• JoshuaEbenezer / FFT-cordic-HDL
  FFT implementation using CORDIC algorithm written in Verilog.
  ☆33Updated 6 years ago
• DOUDIU / AXIS-AXI4-AXIS
  This project is designed to delay the output of the video stream in AXI-STREAM format.
  ☆11Updated 11 months ago
• TheMozg / spi-amba-simulation
  ITMO SystemC & Verilog assignments - AMBA AHB and SPI
  ☆21Updated 7 years ago
• praveenkhemalapure / DDR3-controller-verification
  DDR3 function verification environment in UVM
  ☆25Updated 7 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆36Updated 4 years ago
• cam-n / human-detection-hog-svm
  A human detection system is developed on Matlab and FPGA: The 130x66 RGB pixels of static input image was attracted features and classifi…
  ☆11Updated 2 years ago
• JefferyLi0903 / MMC
  MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计
  ☆22Updated 2 years ago
• xycfwrj / zynq_axi_ddr_barebone
  minimal code to access ps DDR from PL
  ☆20Updated 5 years ago
• Verdvana / Async_FIFO
  位宽和深度可定制的异步FIFO
  ☆13Updated last year
• briansune / FFT-R22SDF
  R22SDF FFT VLSI/FPGA investigate and implementation
  ☆15Updated 3 years ago
• Yongxiang-Guo / Verilog_spi_flash
  SPI通信实现FLASH读写
  ☆14Updated 5 years ago