Alternatives and similar repositories for fpga_labs_sp22:

Users that are interested in fpga_labs_sp22 are comparing it to the libraries listed below

• EECS150 / asic_labs_sp22
  ☆22Updated 2 years ago
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆56Updated last year
• kunalg123 / icc2_workshop_collaterals
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…
  ☆30Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆60Updated last year
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• thuCGRA / SpinalHDL_Chinese_Doc
  Translated SpinalHDL-Doc(v1.7.2) into Chinese
  ☆48Updated last year
• abdelrhman-oun / DDR5_PHY_WriteOperation
  ☆47Updated 2 years ago
• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆53Updated 2 weeks ago
• bojackchen / digital-flow
  This is a tutorial on standard digital design flow
  ☆75Updated 3 years ago
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆51Updated 3 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆48Updated 10 months ago
• erihsu / INT_FP_MAC
  INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.
  ☆97Updated 4 years ago
• esynr3z / axi_vip_demo
  Xilinx AXI VIP example of use
  ☆34Updated 3 years ago
• omega-rg / Cache-Controller
  Two Level Cache Controller implementation in Verilog HDL
  ☆41Updated 4 years ago
• pulp-platform / fpu
  ☆42Updated 6 years ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆52Updated 7 months ago
• ljgibbslf / basic_cache_core
  ☆26Updated 4 years ago
• Centre-for-Hardware-Security / asap7_reference_design
  reference block design for the ASAP7nm library in Cadence Innovus
  ☆41Updated 9 months ago
• siyueyinghua / UVMInPracticesByZhangQiang
  《UVM实战》书本源代码和UVM 1.1d源码及Doc
  ☆35Updated 4 years ago
• ShonTaware / SRAM_SKY130
  Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns
  ☆66Updated 3 years ago
• sheldonucr / ee260_lab
  EE 260 Winter 2017: Advanced VLSI Design
  ☆62Updated 8 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• abdelazeem201 / ICC2_scripts
  This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of ORCA which was taped-out by NTI.
  ☆16Updated last year
• hyf6661669 / Synopsys-Documents
  Some useful documents of Synopsys
  ☆70Updated 3 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆90Updated 5 months ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆72Updated 10 years ago
• suoglu / Fixed-Floating-Point-Adder-Multiplier
  16-bit Adder Multiplier hardware on Digilent Basys 3
  ☆70Updated last year
• schoeberl / chisel-empty
  An almost empty chisel project as a starting point for hardware design
  ☆30Updated 2 months ago
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆74Updated 7 years ago
• AmeerAbdelhadi / Multiported-RAM
  Modular Multi-ported SRAM-based Memory
  ☆29Updated 4 months ago