EECS150 / fpga_labs_sp22
☆25Updated 2 years ago
Related projects ⓘ
Alternatives and complementary repositories for fpga_labs_sp22
- ☆26Updated 5 years ago
- ☆18Updated 2 years ago
- Translated SpinalHDL-Doc(v1.7.2) into Chinese☆47Updated last year
- Two Level Cache Controller implementation in Verilog HDL☆36Updated 4 years ago
- a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…☆56Updated 10 months ago
- ☆25Updated 4 years ago
- This repository has a list of collaterals needed for ICC2 workshop. It has a modified version of raven_soc which was taped-out by Efables…☆28Updated 4 years ago
- INT8 & FP16 multiplier accumulator (MAC) design with UVM verification completed.☆83Updated 4 years ago
- Some useful documents of Synopsys☆49Updated 3 years ago
- A verilog implementation for Network-on-Chip☆67Updated 6 years ago
- This is a tutorial on standard digital design flow☆73Updated 3 years ago
- Base on Synopsys platform using VCS,DC,ICC,PT.☆11Updated 3 years ago
- eyeriss-chisel3☆39Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆58Updated last month
- Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).☆48Updated 5 months ago
- Advanced Architecture Labs with CVA6☆49Updated 10 months ago
- Xilinx AXI VIP example of use☆32Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- Pure digital components of a UCIe controller☆48Updated 2 weeks ago
- ☆37Updated 5 years ago
- ☆67Updated 10 years ago
- Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra☆47Updated 2 years ago
- reference block design for the ASAP7nm library in Cadence Innovus☆32Updated 4 months ago
- EE 260 Winter 2017: Advanced VLSI Design☆58Updated 7 years ago
- An AXI4 crossbar implementation in SystemVerilog☆123Updated last week
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆71Updated 5 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆19Updated 5 years ago
- A Fast, Low-Overhead On-chip Network☆137Updated 3 weeks ago
- AXI4 and AXI4-Lite interface definitions☆83Updated 4 years ago
- HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.☆68Updated 6 years ago