☆35Mar 16, 2022Updated 3 years ago
Alternatives and similar repositories for fpga_labs_sp22
Users that are interested in fpga_labs_sp22 are comparing it to the libraries listed below
Sorting:
- ☆20Dec 11, 2022Updated 3 years ago
- ☆12May 21, 2024Updated last year
- Digital Design Labs☆25Dec 21, 2018Updated 7 years ago
- SDRAM controller for MIPSfpga+ system☆24Oct 30, 2020Updated 5 years ago
- Documents for ARM☆35May 8, 2025Updated 10 months ago
- A small 32-bit implementation of the RISC-V architecture☆32Jul 17, 2020Updated 5 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆38Jun 2, 2021Updated 4 years ago
- ☆10Oct 23, 2016Updated 9 years ago
- ☆11Oct 10, 2018Updated 7 years ago
- ☆11Apr 3, 2017Updated 8 years ago
- NJUCS 2023 Spring DLCO 南京大学 数字逻辑与计算机组成 课程实验☆30Mar 5, 2025Updated last year
- Open Component Portability Infrastructure☆62May 1, 2021Updated 4 years ago
- Dweb 2FA Client☆13Feb 16, 2024Updated 2 years ago
- ☆12Aug 26, 2016Updated 9 years ago
- Alpha64 R10000 Two-Way Superscalar Processor☆11May 6, 2019Updated 6 years ago
- Main repo of the OOP class☆11Oct 16, 2017Updated 8 years ago
- Inverse Quantum-Optical Design of High-Dimensional Qudits☆17Aug 2, 2022Updated 3 years ago
- A Fractional Divider with Delta-Sigma Modulator and Dual-Mode Divider for Phase-Locked Loop☆16Apr 25, 2021Updated 4 years ago
- cslib for The Art and Science of C and Programming Abstractions in C by @eric-roberts☆13Aug 24, 2023Updated 2 years ago
- hadoop 的 docker 集群配置☆10Jun 8, 2024Updated last year
- RTL Design and Implementation of High Performance Algorithm Logic Units☆15Oct 1, 2019Updated 6 years ago
- A tool for modeling FSMs by VHDL or Verilog☆11Mar 1, 2026Updated last week
- Sargon Chess for CP/M☆11May 12, 2021Updated 4 years ago
- BlueDBM hw/sw implementation using the bluespecpcie PCIe library☆12Dec 25, 2022Updated 3 years ago
- Design and optimize variational quantum sensors☆11Dec 10, 2024Updated last year
- Dadda multiplier(8*8, 16*16, 32*32) in Verilog HDL.☆42Jun 6, 2024Updated last year
- ☆47Jul 16, 2025Updated 7 months ago
- FFT algorithm coded in Verilog. Designed to run on a Xillinx Spartan 6 FPGA board.☆15Jul 19, 2012Updated 13 years ago
- AltOr32 - Alternative Lightweight OpenRisc CPU☆13Dec 17, 2015Updated 10 years ago
- 6-stage dual-issue in-order superscalar risc-v cpu with floating point unit☆14Updated this week
- This repository integrates gem5 with Ramulator2, allowing gem5 to use Ramulator2 as its DRAM memory model. With the provided materials an…☆13Jun 7, 2025Updated 9 months ago
- Deprecated - This library has been replaced by OsvvmLibraries. The links to the submodules will not be updated to the new versions.☆10Jul 22, 2020Updated 5 years ago
- Integration test of Verilog AXI modules (https://github.com/alexforencich/verilog-axi) with LiteX.☆17Dec 19, 2022Updated 3 years ago
- Windows 2000 Source Code☆11Aug 3, 2024Updated last year
- ☆12May 29, 2020Updated 5 years ago
- Python program that generates the hologram of a phase-only SLM to produce a desired (phase and amplitude) mode profile, as described in h…☆11Jun 23, 2020Updated 5 years ago
- FPGA Guide☆14Jan 2, 2022Updated 4 years ago
- 开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…☆13Mar 10, 2019Updated 6 years ago
- 位宽和深度可定制的异步FIFO☆14May 29, 2024Updated last year