Dmitriy0111 / nanoFOX_VHDL
A small RISC-V core (VHDL)
☆7Updated 5 years ago
Alternatives and similar repositories for nanoFOX_VHDL:
Users that are interested in nanoFOX_VHDL are comparing it to the libraries listed below
- ☆17Updated 2 years ago
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated last year
- ☆33Updated 2 years ago
- SystemVerilog IPs and Modules for architectural redundancy designs.☆12Updated last month
- ☆25Updated this week
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated 2 years ago
- Open Source AES☆31Updated last year
- Platform Level Interrupt Controller☆38Updated 10 months ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆48Updated 2 months ago
- TileLink Uncached Lightweight (TL-UL) implementation on Chisel.☆20Updated 4 years ago
- The ParaNut Processor - Highly Parallel and More Than Just a CPU Core☆33Updated last year
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆18Updated 2 years ago
- ☆36Updated 2 years ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆30Updated 11 months ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆32Updated 3 weeks ago
- LunaPnR is a place and router for integrated circuits☆46Updated 4 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆19Updated 3 years ago
- AHB-Lite based SoC for IBEX/SWERV/VEXRISC/...☆13Updated last week
- ☆11Updated 2 weeks ago
- 2-8bit weights, 8-bit activations flexible Neural Processing Engine for PULP clusters☆24Updated last week
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆33Updated 4 years ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated 2 years ago
- HW-SW Co-Simulation Library for AMBA AXI BFM using DPI/VPI☆31Updated 3 months ago
- This document adopts the method from the XAPP1230 for doing readback capture on Xilinx UltraScale devices and shows how to migrate the sa…☆16Updated 5 years ago
- Source-Opened RISCV for Crypto☆15Updated 3 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆40Updated last year
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆13Updated 4 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆70Updated 11 months ago
- RISC-V soft-core PEs for TaPaSCo☆18Updated 9 months ago