Dmitriy0111 / nanoFOX_VHDLLinks
A small RISC-V core (VHDL)
☆7Updated 5 years ago
Alternatives and similar repositories for nanoFOX_VHDL
Users that are interested in nanoFOX_VHDL are comparing it to the libraries listed below
Sorting:
- RISC-V soft-core PEs for TaPaSCo☆22Updated last year
- RISCV core RV32I/E.4 threads in a ring architecture☆32Updated 2 years ago
- Procyon is the brightest star in the constellation of Canis Minor. But it's also the name of my RISC-V out-of-order processor.☆12Updated 2 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆21Updated 2 years ago
- APB Logic☆18Updated 7 months ago
- Design, verification and ASIC implementation of a complete RISC-V CPU with: five stages pipeline, forwarding, automatic hazard detection,…☆15Updated 5 years ago
- ☆17Updated 2 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆45Updated 3 years ago
- Repository for Hornet RISC-V Core☆18Updated 2 years ago
- Technology dependent cells instantiated in the design for generic process (simulation, FPGA)☆62Updated 5 months ago
- Dual-issue RV64IM processor for fun & learning☆62Updated 2 years ago
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆23Updated 2 years ago
- ☆33Updated 2 years ago
- ☆37Updated 3 years ago
- A Python package for generating HDL wrappers and top modules for HDL sources☆33Updated last week
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Updated 4 years ago
- ArmleoCPU - RISC-V CPU RV64GC, SMP, Linux, Doom. Work in progress to execute first instruction with new feature set☆6Updated 2 years ago
- ☆30Updated this week
- SystemVerilog IPs and Modules for architectural redundancy designs.☆14Updated last week
- A padring generator for ASICs☆25Updated 2 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- Tightly-coupled cache coherence unit for CVA6 using the ACE protocol☆36Updated last year
- LunaPnR is a place and router for integrated circuits☆47Updated 7 months ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆42Updated 2 years ago
- Library of open source Process Design Kits (PDKs)☆48Updated 3 weeks ago
- RiftCore is a 9-stage, single-issue, out-of-order 64-bits RISC-V Core, which supports RV64IMC and 3-level Cache System☆42Updated 2 years ago
- Digital Hardware Modelling using VHDL, Verilog, SystemVerilog, SystemC, HLS(C++, OpenCL)☆66Updated 5 months ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆30Updated 4 years ago
- DUTH RISC-V Superscalar Microprocessor☆31Updated 8 months ago
- HARV - HArdened Risc-V☆14Updated 3 years ago