louisliuwei / FPGA-Design-Flow-using-Vivado

Related projects: ⓘ

• alexforencich / xfcp
  Extensible FPGA control platform
  ☆52Updated last year
• SparcLab / OpenSERDES
  Digitally synthesizable architecture for SerDes using Skywater Open PDK 130 nm technology.
  ☆137Updated 2 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆28Updated this week
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆94Updated last year
• airhdl / spi-to-axi-bridge
  An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.
  ☆40Updated 9 months ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆40Updated 2 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆38Updated 2 years ago
• alexforencich / fpga-utils
  Various utilities for working with FPGAs
  ☆10Updated 8 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆39Updated 6 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 6 years ago
• ultraembedded / core_dbg_bridge
  UART -> AXI Bridge
  ☆52Updated 3 years ago
• suoto / fpga_cores
  ☆32Updated last year
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆25Updated 3 years ago
• hellgate202 / csi2_rx
  MIPI CSI-2 RX
  ☆28Updated 2 years ago
• buttercutter / DDR
  A simple DDR3 memory controller
  ☆49Updated last year
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆53Updated 4 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆55Updated last year
• ultraembedded / core_soc
  Basic Peripheral SoC (SPI, GPIO, Timer, UART)
  ☆57Updated 4 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆53Updated 4 months ago
• CESNET / ofm
  Open FPGA Modules
  ☆22Updated last week
• slaclab / ruckus
  Vivado build system
  ☆68Updated last week
• antmicro / cocotb-verilator-build
  ☆25Updated last year
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆19Updated 6 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆28Updated 5 years ago
• alexforencich / cocotbext-eth
  Ethernet interface modules for Cocotb
  ☆53Updated 10 months ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆95Updated 8 months ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆75Updated 4 years ago
• ahmedshahein / DSP-RTL-Lib
  RTL Verilog library for various DSP modules
  ☆80Updated 2 years ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆37Updated last year
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆21Updated 9 months ago