ikwzm / FPGA-SoC-Linux
FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq-Zybo:PYNQ-Z1 Altera:de0-nano-soc:de10-nano)
☆161Updated last year
Alternatives and similar repositories for FPGA-SoC-Linux:
Users that are interested in FPGA-SoC-Linux are comparing it to the libraries listed below
- FPGA+SoC+Linux+Device Tree Overlay+FPGA Manager U-Boot&Linux Kernel&Debian11 Images (for Xilinx:Zynq Ultrascale+ MPSoC)☆130Updated last year
- ☆62Updated 7 years ago
- ☆111Updated last week
- Avnet Board Definition Files☆132Updated 2 months ago
- ☆124Updated 2 months ago
- Collection of Yocto Project layers to enable AMD Xilinx products☆153Updated 3 weeks ago
- Example designs for FPGA Drive FMC☆238Updated 2 months ago
- ☆67Updated last week
- meta-petalinux distro layer supporting Xilinx Tools☆88Updated 2 months ago
- SystemC/TLM-2.0 Co-simulation framework☆238Updated 4 months ago
- Linux device tree generator for the Xilinx SDK (Vivado > 2014.1)☆208Updated 4 months ago
- RISC-V Integration for PYNQ☆170Updated 5 years ago
- Source code from the MicroZed Chronicles blog hosted by Xcell Daily Blog☆190Updated 6 years ago
- Hardware, Linux Driver and Library for the Zynq AXI DMA interface☆100Updated 6 years ago
- This is a wiki and code sharing for ZYNQ☆71Updated 8 years ago
- Repository used to support automated builds under PetaLinux tools that use Yocto.☆59Updated last week
- Examples using the Cyclone V SoC chip☆106Updated 5 years ago
- Verilog implementation of a RISC-V core☆109Updated 6 years ago
- Example design for the Ethernet FMC using the hard GEMs of the Zynq☆54Updated 4 months ago
- ☆54Updated 2 years ago
- Board files to build Ultra 96 PYNQ image☆154Updated 3 months ago
- Raspberry Pi v2 camera (IMX219) to DisplayPort of Ultra96-V2 board through PL☆69Updated 3 years ago
- A simple, basic, formally verified UART controller☆294Updated last year
- ☆279Updated last week
- Verilog digital signal processing components☆129Updated 2 years ago
- Files used with hackster examples☆144Updated 4 years ago
- Tool to generate register RTL, models, and docs using SystemRDL or JSpec input☆198Updated 5 months ago
- Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.☆63Updated last month
- ☆68Updated 8 months ago
- Generates Makefiles to synthesize, place, and route verilog using Vivado☆94Updated 2 years ago