fpgadeveloper / ethernet-fmc-zynq-gem

Related projects: ⓘ

• fpgadeveloper / ethernet-fmc-axi-eth
  Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks
  ☆62Updated 10 months ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆75Updated 4 years ago
• alexforencich / corundum
  Open source FPGA-based NIC and platform for in-network compute
  ☆53Updated 4 months ago
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆60Updated 3 months ago
• lewiz-support / LMAC_CORE3
  Ethernet MAC IP Core for 100G/50G/40G/25G/10Gbps
  ☆37Updated last year
• h-nasiri / Zynq-Linux-DMA
  DMA enabled Zynq PS-PL communication to implement high throughput data transfer between Linux applications and user IP core.
  ☆36Updated 7 years ago
• fpgadeveloper / zedboard-axi-dma
  Demonstration of the AXI DMA engine on the ZedBoard
  ☆50Updated 3 years ago
• antmicro / nvme-verilog-pcie
  ☆43Updated 2 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆52Updated last year
• RHSResearchLLC / XilinxAR65444
  Repository for Xilinx PCIe DMA drivers
  ☆39Updated 6 years ago
• mcjtag / eth_switch
  Verilog Ethernet Switch (layer 2)
  ☆30Updated 11 months ago
• CospanDesign / nysa-sata
  ☆79Updated 7 years ago
• olofk / fifo
  Generic FIFO implementation with optional FWFT
  ☆53Updated 4 years ago
• fpgadeveloper / microzed-axi-dma
  Demonstration of the AXI DMA engine on the MicroZed
  ☆26Updated 3 years ago
• OVGN / OpenHBMC
  Open-source high performance AXI4-based HyperRAM memory controller
  ☆55Updated last year
• aquaxis / gemac
  Gigabit MAC + UDP/TCP/IP offload Engine
  ☆30Updated 5 years ago
• bmartini / zynq-axis
  Hardware, Linux Driver and Library for the Zynq AXI DMA interface
  ☆98Updated 6 years ago
• Avnet / hdl
  ☆105Updated last week
• pulp-platform / axi_spi_slave
  ☆21Updated 3 years ago
• forconesi / nfmac10g
  Open source 10 Gigabit Ethernet MAC core compatible with Xilinx's non-free 10GMAC
  ☆60Updated 7 years ago
• alexforencich / verilog-cam
  Verilog Content Addressable Memory Module
  ☆100Updated 2 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆42Updated 9 years ago
• freecores / xge_mac
  Ethernet 10GE MAC
  ☆44Updated 10 years ago
• imrickysu / ZYNQ-Cookbook
  This is a wiki and code sharing for ZYNQ
  ☆70Updated 8 years ago
• analogdevicesinc / fpgahdl_xilinx
  (RETIRED see https://github.com/analogdevicesinc/hdl instead) FPGA interface reference designs for Analog Devices mixed signal IC product…
  ☆87Updated 6 years ago
• Xilinx-Wiki-Projects / ZCU102-Ethernet
  Ethernet Example Projects targeting the Xilinx ZCU102 evaluation board. This repository replaces XAPP1305.
  ☆53Updated 2 years ago
• intel / fpga-partial-reconfig
  Tutorials, scripts and reference designs for the Intel FPGA partial reconfiguration (PR) design flow
  ☆86Updated 3 months ago
• maswx / vu13p
  国产VU13P加速卡资料
  ☆55Updated 4 months ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆47Updated 5 years ago
• strezh / XPDMA
  PCIe DMA Subsystem based on Xilinx XAPP1171
  ☆45Updated last year