Digilent / digilent-xdc
A collection of Master XDC files for Digilent FPGA and Zynq boards.
☆531Updated 2 months ago
Alternatives and similar repositories for digilent-xdc:
Users that are interested in digilent-xdc are comparing it to the libraries listed below
- ☆408Updated 2 weeks ago
- ☆590Updated 6 months ago
- Verilog AXI stream components for FPGA implementation☆766Updated 5 months ago
- SystemVerilog to Verilog conversion☆584Updated last month
- Bus bridges and other odds and ends☆507Updated last week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,181Updated this week
- Verilog UART☆433Updated last year
- Verilog AXI components for FPGA implementation☆1,583Updated last year
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆559Updated 6 years ago
- Verilog I2C interface for FPGA implementation☆566Updated 6 months ago
- Common SystemVerilog components☆550Updated this week
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆562Updated 4 years ago
- Python-based Hardware Design Processing Toolkit for Verilog HDL☆663Updated 7 months ago
- A git-friendly Vivado wrapper☆221Updated 7 months ago
- A DDR3 memory controller in Verilog for various FPGAs☆387Updated 3 years ago
- 32-bit Superscalar RISC-V CPU☆915Updated 3 years ago
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆585Updated 2 weeks ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆999Updated 5 months ago
- Various HDL (Verilog) IP Cores☆725Updated 3 years ago
- synthesiseable ieee 754 floating point library in verilog☆548Updated last year
- Verilog library for ASIC and FPGA designers☆1,235Updated 8 months ago
- ☆270Updated last month
- lowRISC Style Guides☆384Updated 4 months ago
- Verilog SDRAM memory controller☆313Updated 7 years ago
- SPI Master for FPGA - VHDL and Verilog☆267Updated last year
- The UVM written in Python☆393Updated last week
- Digital Design with Chisel☆795Updated last week
- VUnit is a unit testing framework for VHDL/SystemVerilog☆756Updated this week
- Verilog PCI express components☆1,183Updated 8 months ago
- BaseJump STL: A Standard Template Library for SystemVerilog☆537Updated last week