Digilent / digilent-xdcLinks
A collection of Master XDC files for Digilent FPGA and Zynq boards.
☆592Updated 7 months ago
Alternatives and similar repositories for digilent-xdc
Users that are interested in digilent-xdc are comparing it to the libraries listed below
Sorting:
- ☆444Updated 5 months ago
- lowRISC Style Guides☆436Updated last week
- Bus bridges and other odds and ends☆568Updated 2 months ago
- ☆618Updated 11 months ago
- Verilog UART☆490Updated 3 months ago
- Verilog I2C interface for FPGA implementation☆624Updated 3 months ago
- Various HDL (Verilog) IP Cores☆813Updated 3 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,080Updated 3 weeks ago
- Verilog AXI stream components for FPGA implementation☆810Updated 3 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆667Updated 3 weeks ago
- Common SystemVerilog components☆629Updated this week
- AXI SystemVerilog synthesizable IP modules and verification infrastructure for high-performance on-chip communication☆1,308Updated this week
- A git-friendly Vivado wrapper☆232Updated last year
- SystemVerilog to Verilog conversion☆639Updated last month
- VHDL and Verilog/SV IDE: state machine viewer, linter, documentation, snippets... and more!☆625Updated 2 months ago
- synthesiseable ieee 754 floating point library in verilog☆645Updated 2 years ago
- Digital Design with Chisel☆842Updated last month
- A DDR3 memory controller in Verilog for various FPGAs☆475Updated 3 years ago
- This is the top-level project for the PULPissimo Platform. It instantiates a PULPissimo open-source system with a PULP SoC domain, but no…☆426Updated last month
- A huge collection of VHDL/Verilog open-source IP cores scraped from the web☆499Updated 2 years ago
- ☆288Updated 3 weeks ago
- A huge VHDL library for FPGA and digital ASIC development☆390Updated this week
- UVVM (Universal VHDL Verification Methodology) is a free and Open Source Methodology and Library for very efficient VHDL verification of …☆399Updated last month
- Project F brings FPGAs to life with exciting open-source designs you can build on.☆642Updated 5 months ago
- Repository for basic (and not so basic) Verilog blocks with high re-use potential☆581Updated 7 years ago
- Open Logic FPGA Standard Library☆636Updated this week
- Verilog AXI components for FPGA implementation☆1,746Updated 3 months ago
- IP Core Library - Published and maintained by the Chair for VLSI Design, Diagnostics and Architecture, Faculty of Computer Science, Techn…☆580Updated 4 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆353Updated last year
- Parametric floating-point unit with support for standard RISC-V formats and operations as well as transprecision formats.☆504Updated 4 months ago