Source files for SiFive's Freedom platforms
☆1,145Jul 17, 2026Updated 3 weeks ago
Alternatives and similar repositories for freedom
Users that are interested in freedom are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Common RTL blocks used in SiFive's projects☆193May 13, 2022Updated 4 years ago
- Open Source Software for Developing on the Freedom E Platform - Deprecated☆583Jul 1, 2024Updated 2 years ago
- Rocket Chip Generator☆3,840Jun 2, 2026Updated 2 months ago
- The root repo for lowRISC project and FPGA demos.☆602Aug 3, 2023Updated 3 years ago
- SonicBOOM: The Berkeley Out-of-Order Machine☆2,213Jul 22, 2026Updated 2 weeks ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Support for Rocket Chip on Zynq FPGAs☆422Jan 29, 2019Updated 7 years ago
- Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2☆2,850Mar 24, 2021Updated 5 years ago
- An open-source microcontroller system based on RISC-V☆1,057Feb 6, 2024Updated 2 years ago
- RISC-V Tools (ISA Simulator and Tests)☆1,194Dec 22, 2022Updated 3 years ago
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆2,350Jul 29, 2026Updated last week
- The CORE-V CVA6 is a highly configurable, 6-stage RISC-V core for both application and embedded applications. Application class configura…☆3,060Updated this week
- Chisel: A Modern Hardware Design Language☆4,754Updated this week
- PicoRV32 - A Size-Optimized RISC-V CPU☆4,309Jul 31, 2026Updated last week
- chisel tutorial exercises and answers☆757Jan 6, 2022Updated 4 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- Flexible Intermediate Representation for RTL☆748Aug 20, 2024Updated last year
- Freedom U Software Development Kit (FUSDK)☆304Updated this week
- A FPGA friendly 32 bit RISC-V CPU implementation☆3,218Feb 11, 2026Updated 5 months ago
- educational microarchitectures for risc-v isa☆753Sep 1, 2025Updated 11 months ago
- Comment on the rocket-chip source code☆179Oct 19, 2018Updated 7 years ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆992Nov 15, 2024Updated last year
- FireSim: Fast and Effortless FPGA-accelerated Hardware Simulation with On-Prem and Cloud Flexibility☆1,032Jun 26, 2026Updated last month
- A directory of Western Digital’s RISC-V SweRV Cores☆882Mar 26, 2020Updated 6 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆1,274May 29, 2026Updated 2 months ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- A 32-bit Microcontroller featuring a RISC-V core☆164Feb 28, 2018Updated 8 years ago
- Ibex is a small 32-bit RISC-V CPU core with high-level of verification (previously known as zero-riscy)☆2,004Jul 28, 2026Updated last week
- Package manager and build abstraction tool for FPGA/ASIC development☆1,446Updated this week
- Tools for SiFive's Freedom Platform☆218Aug 26, 2021Updated 4 years ago
- Spike, a RISC-V ISA Simulator☆3,189Updated this week
- VeeR EH1 core☆960Jul 16, 2026Updated 3 weeks ago
- RISC-V Proxy Kernel☆705Oct 2, 2025Updated 10 months ago
- RISC-V CPU Core☆443Jun 24, 2025Updated last year
- Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel☆223Jan 23, 2020Updated 6 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Random instruction generator for RISC-V processor verification☆1,337Apr 3, 2026Updated 4 months ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆693Jul 16, 2025Updated last year
- RTL, Cmodel, and testbench for NVDLA☆2,134Mar 2, 2022Updated 4 years ago
- A Library of Chisel3 Tools for Digital Signal Processing☆249Apr 29, 2024Updated 2 years ago
- Simple RISC-V 3-stage Pipeline in Chisel☆619Aug 9, 2024Updated 2 years ago
- ☆139May 13, 2022Updated 4 years ago
- IC design and development should be faster，simpler and more reliable☆2,006Dec 31, 2021Updated 4 years ago