sifive / freedom
Source files for SiFive's Freedom platforms
☆1,111Updated 3 years ago
Related projects ⓘ
Alternatives and complementary repositories for freedom
- SonicBOOM: The Berkeley Out-of-Order Machine☆1,736Updated last month
- VeeR EH1 core☆818Updated last year
- Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.☆1,371Updated last month
- RISC-V Tools (ISA Simulator and Tests)☆1,144Updated last year
- chisel tutorial exercises and answers☆694Updated 2 years ago
- CV32E40P is an in-order 4-stage RISC-V RV32IMFCXpulp CPU based on RI5CY from PULP-Platform☆959Updated 3 months ago
- Open Source Software for Developing on the Freedom E Platform - Deprecated☆581Updated 4 months ago
- The root repo for lowRISC project and FPGA demos.☆597Updated last year
- educational microarchitectures for risc-v isa☆687Updated 2 months ago
- An open-source microcontroller system based on RISC-V☆890Updated 9 months ago
- The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux☆2,273Updated this week
- Rocket Chip Generator☆3,251Updated last week
- An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more☆1,639Updated this week
- mor1kx - an OpenRISC 1000 processor IP core☆494Updated 3 weeks ago
- Portable RISC-V System-on-Chip implementation: RTL, debugger and simulators☆624Updated last week
- Random instruction generator for RISC-V processor verification☆1,017Updated 2 months ago
- A FPGA friendly 32 bit RISC-V CPU implementation☆2,501Updated 2 weeks ago
- ☆891Updated this week
- RISC-V Cores, SoC platforms and SoCs☆836Updated 3 years ago
- A small, light weight, RISC CPU soft core☆1,299Updated 3 weeks ago
- Flexible Intermediate Representation for RTL☆729Updated 2 months ago
- SCR1 is a high-quality open-source RISC-V MCU core in Verilog☆860Updated last month
- Verilog library for ASIC and FPGA designers☆1,183Updated 6 months ago
- Generator Bootcamp Material: Learn Chisel the Right Way☆976Updated last month
- A directory of Western Digital’s RISC-V SweRV Cores☆855Updated 4 years ago
- OpenXuantie - OpenC910 Core☆1,161Updated 4 months ago
- The OpenPiton Platform☆642Updated 3 weeks ago
- opensouce RISC-V cpu core implemented in Verilog from scratch in one night!☆2,115Updated 3 weeks ago
- PicoRV32 - A Size-Optimized RISC-V CPU☆3,132Updated 4 months ago
- 32-bit Superscalar RISC-V CPU☆863Updated 3 years ago