Alternatives and similar repositories for OpenC910_Modified

Users that are interested in OpenC910_Modified are comparing it to the libraries listed below

• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆224Updated 2 years ago
• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆104Updated 5 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆121Updated 11 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆182Updated 7 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆107Updated 4 years ago
• troyguo / awesome-dv
  Awesome ASIC design verification
  ☆329Updated 3 years ago
• funningboy / uvm_axi
  uvm AXI BFM(bus functional model)
  ☆261Updated 12 years ago
• WilsonChen003 / HDLGen
  HDLGen is an HDL generation tool, supporting embedded Perl or Python script, reduce manual work & improve effiency with a few embedded f…
  ☆106Updated last year
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆87Updated last month
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆129Updated 7 years ago
• wudayemen / gen_apb_file
  ☆74Updated 4 years ago
• Practical-UVM-Step-By-Step / Practical-UVM-Step-By-Step
  This is the main repository for all the examples for the book Practical UVM
  ☆206Updated 5 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆165Updated 3 years ago
• ForrestBlue / cortexm0ds
  ☆69Updated 9 years ago
• flyskywalker / ahb_sramc
  ahb scram controller, design and verification
  ☆27Updated 7 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆132Updated 4 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆155Updated 5 years ago
• hellovimo / uvm_testbench_gen
  Novel GUI Based UVM Testbench Template Builder
  ☆144Updated 4 years ago
• brentwang-lab / uvm_tb_gen
  This is for uvm_tb_gen
  ☆42Updated 8 months ago
• taichi-ishitani / tvip-axi
  AMBA AXI VIP
  ☆426Updated last year
• RV-BOSC / OpenNoC
  ☆199Updated 4 months ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆45Updated 5 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆55Updated 6 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆109Updated 7 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆109Updated 9 months ago
• mayurkubavat / UVM-Examples
  UVM examples and projects
  ☆147Updated 4 months ago
• kumarrishav14 / AXI
  VIP for AXI Protocol
  ☆155Updated 3 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆387Updated last month
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆149Updated 7 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆37Updated 5 years ago