Advanced-Microelectronics-Group / OpenC910_ModifiedLinks
commit rtl and build cosim env
☆35Updated last year
Alternatives and similar repositories for OpenC910_Modified
Users that are interested in OpenC910_Modified are comparing it to the libraries listed below
Sorting:
- AMBA bus generator including AXI4, AXI3, AHB, and APB☆209Updated 2 years ago
- AXI DMA 32 / 64 bits☆115Updated 11 years ago
- AXI总线连接器☆100Updated 5 years ago
- AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…☆173Updated 6 years ago
- ☆72Updated 3 years ago
- This is the main repository for all the examples for the book Practical UVM☆199Updated 4 years ago
- ☆67Updated 9 years ago
- uvm AXI BFM(bus functional model)☆250Updated 12 years ago
- AMBA bus lecture material☆448Updated 5 years ago
- Awesome ASIC design verification☆311Updated 3 years ago
- AXI协议规范中文翻译版☆153Updated 3 years ago
- A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog☆354Updated last year
- ☆147Updated 3 weeks ago
- automatic-verilog based on vimscript☆266Updated last year
- AMBA bus generator including AXI, AHB, and APB☆105Updated 3 years ago
- yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/☆121Updated 7 years ago
- Cortex M0 based SoC☆73Updated 3 years ago
- Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.☆127Updated 4 years ago
- SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core☆144Updated 7 years ago
- CPU Design Based on RISCV ISA☆117Updated last year
- AMBA AXI VIP☆410Updated last year
- UVM examples and projects☆140Updated 2 weeks ago
- ahb scram controller, design and verification☆27Updated 7 years ago
- Novel GUI Based UVM Testbench Template Builder☆138Updated 4 years ago
- Step by step tutorial for building CortexM0 SoC☆38Updated 3 years ago
- AMBA AHB 2.0 VIP in SystemVerilog UVM☆151Updated 5 years ago
- Some useful documents of Synopsys☆76Updated 3 years ago
- 视频旋转(2019FPGA大赛)☆34Updated 5 years ago
- System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment☆105Updated 6 months ago
- UVM AHB VIP☆86Updated 7 months ago