Alternatives and similar repositories for OpenC910_Modified

Users that are interested in OpenC910_Modified are comparing it to the libraries listed below

• Verdvana / AXI4_Interconnect
  AXI总线连接器
  ☆97Updated 5 years ago
• freecores / dma_axi
  AXI DMA 32 / 64 bits
  ☆114Updated 10 years ago
• marcoz001 / axi-uvm
  yet another AXI testbench repo. ;) This is for my UVM practice. https://marcoz001.github.io/axi-uvm/
  ☆119Updated 7 years ago
• courageheart / AMBA_APB_SRAM
  AMBA v.3 APB v.1 Specification Complaint Slave SRAM Core design and testbench. The testbench is developed using System Verilog and UVM an…
  ☆172Updated 6 years ago
• wudayemen / gen_apb_file
  ☆70Updated 3 years ago
• adki / gen_amba_2021
  AMBA bus generator including AXI4, AXI3, AHB, and APB
  ☆205Updated last year
• flyskywalker / ahb_sramc
  ahb scram controller, design and verification
  ☆27Updated 6 years ago
• ForrestBlue / cortexm0ds
  ☆64Updated 9 years ago
• adki / gen_amba
  AMBA bus generator including AXI, AHB, and APB
  ☆101Updated 3 years ago
• seabeam / yuu_ahb
  UVM AHB VIP
  ☆85Updated 6 months ago
• xiaoerlang0359 / E203plus
  upgrade to e203 (a risc-v core)
  ☆44Updated 4 years ago
• lucky-wfw / ARM_AMBA_Design
  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.
  ☆126Updated 4 years ago
• emwzq / example_uvm
  UVM实战随书源码
  ☆51Updated 6 years ago
• flyjancy / CortexM0_SoC
  Cortex M0 based SoC
  ☆73Updated 3 years ago
• KasuganoSoraaa / simple-AXI2AHB-bridge
  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc
  ☆42Updated 3 years ago
• Lianghao-Yuan / AHB_Bus_Matrix
  ☆36Updated 9 years ago
• lizhirui / AXI_spec_chinese
  AXI协议规范中文翻译版
  ☆150Updated 2 years ago
• wangjidwb123 / AHB-SRAMC
  IC Verification & SV Demo
  ☆54Updated 3 years ago
• gupta409 / Processor-UVM-Verification
  System Verilog based Verification of MIPS 5 staged pipelined processor using UVM environment
  ☆103Updated 5 months ago
• flyjancy / CortexM0_SoC_Task
  Step by step tutorial for building CortexM0 SoC
  ☆38Updated 3 years ago
• Verdvana / AXI_SRAM
  支持AXI总线协议的8k×8 SP SRAM
  ☆25Updated 5 years ago
• Travissss / ahb2apb-bridge
  An uvm verification env for ahb2apb bridge
  ☆53Updated 4 years ago
• GodelMachine / AHB2
  AMBA AHB 2.0 VIP in SystemVerilog UVM
  ☆150Updated 5 years ago
• RoaLogic / ahb3lite_interconnect
  AHB3-Lite Interconnect
  ☆89Updated last year
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆94Updated 4 years ago
• andres-mancera / ethernet_10ge_mac_SV_UVM_tb
  SystemVerilog-based UVM testbench for an Ethernet 10GE MAC core
  ☆142Updated 6 years ago
• nelsoncsc / ISP_UVM
  A Framework for Design and Verification of Image Processing Applications using UVM
  ☆100Updated 7 years ago
• zhajio1988 / Open_RegModel
  Use ORDT and systemRDL tools to generate C/Verilog header files, register RTL, UVM register models, and docs from compiled SystemRDL.
  ☆69Updated 5 years ago
• twomonkeyclub / UART
  ARM中通过APB总线连接的UART模块
  ☆67Updated 5 years ago
• seabeam / yuu_apb
  UVM APB VIP, part of AMBA3&AMBA4 feature supported
  ☆31Updated 4 years ago