CherryYang05 / OpenMIPS_CPU
基于龙芯 OpenMIPS 实现一个具有 89 条指令的五级流水 CPU，使用 Verilog 语言，使用哈佛结构，包括逻辑移位指令、乘除法指令、加载存储指令、转移指令、协处理器访问指令以及异常相关在内的共89条指令。能够处理数据相关，包含流水线暂停以及延迟槽
☆19Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for OpenMIPS_CPU
- 复旦大学FDU1.1队在第四届“龙芯杯”的参赛作品☆40Updated 4 years ago
- UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.☆121Updated 5 months ago
- a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog☆45Updated 11 months ago
- 为了更好地帮助后来的同学参加龙芯杯，草拟了这份建议，望对后来人有所帮助☆114Updated 4 years ago
- LLCL-MIPS is a superscalar MIPS processor, which supports MIPS Release 1 instructions and is capable of booting linux kernel. （第五届龙芯杯特等奖作…☆35Updated 2 years ago
- ☆33Updated 5 years ago
- 龙芯杯21个人赛作品☆34Updated 3 years ago
- Highly configurable out-of-order MIPS32 processor, capable of booting Linux.☆37Updated last year
- 体系结构课程实验：RISC-V 32I 流水线 CPU，实现37条指令，转发，冒险检测，Cache，分支预测器☆65Updated 4 years ago
- Introduction to Computer Systems (II), Spring 2021☆48Updated 3 years ago
- High performance LA32R out-of-order processor core. (NSCSCC 2023 Special Prize)☆69Updated last year
- ☆31Updated last year
- NSCSCC 信息整合☆220Updated 3 years ago
- A LoongArch pipeline CPU. Project of Computer Architecture Lab @UCAS.☆17Updated 5 months ago
- A Verilator based SoC simulator that allows you to define AXI Slave interface in software.☆43Updated 3 weeks ago
- 国科大一生一芯第二期: RISCV-64 五级流水线CPU☆15Updated 3 years ago
- A softcore microprocessor of MIPS32 architecture.☆39Updated 4 months ago
- NSCSCC 2020 - Yet Another MIPS Processor☆14Updated 3 years ago
- CQU Dual Issue Machine☆34Updated 5 months ago
- Chongqing University 2020 NSCSCC☆28Updated 4 years ago
- 一个单发射五级静态流水CPU，采用龙芯32位精简版指令集，支持异常和中断处理，使用AXI总线接口，已集成TLB模块☆12Updated last year
- Asymmetric dual issue in-order microprocessor.☆34Updated 5 years ago
- 2022年龙芯杯个人赛 单发射110M（含icache）☆43Updated 2 years ago
- 我的一生一芯项目☆16Updated 2 years ago
- Linux-capable out-of-order superscaler multicore LoongArch32 (LA32 / LA32R) processor.☆14Updated 3 months ago
- ☆50Updated 4 years ago
- Verilog实现单周期非流水线32位RISCV指令集（45条）CPU☆35Updated 3 years ago
- Naïve MIPS32 SoC implementation☆113Updated 4 years ago
- 适用于龙芯杯团队赛入门选手的应急cache模块☆22Updated 8 months ago
- A toy compiler that translates SysY (a subset of C language) into ARMv7a assembly.☆12Updated 3 years ago