Alternatives and similar repositories for liquid-router:

Users that are interested in liquid-router are comparing it to the libraries listed below

• TI-Bonn / vercolib_pcie
  VHDL PCIe Transceiver
  ☆28Updated 4 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆39Updated 2 months ago
• subutai-attic / pars
  ☆29Updated 8 years ago
• micro-FPGA / engine-V
  SoftCPU/SoC engine-V
  ☆54Updated 3 weeks ago
• ultraembedded / core_enet
  Ethernet MAC 10/100 Mbps
  ☆26Updated 3 years ago
• rprinz08 / arty-s7-multinic
  ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface
  ☆13Updated 4 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆79Updated 5 years ago
• azonenberg / antikernel-ipcores
  FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations
  ☆62Updated this week
• jsyk / miilink
  Connecting FPGA and MCU using Ethernet RMII
  ☆23Updated 9 years ago
• freecores / turbo8051
  turbo 8051
  ☆29Updated 7 years ago
• pbing / USB
  FPGA USB 1.1 Low-Speed Implementation
  ☆34Updated 6 years ago
• coltonshane / WAVE-Vivado
  HDL and C source for WAVE Zynq Ultrascale+ SoC
  ☆18Updated 3 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆89Updated 4 years ago
• hamsternz / ArtyEtherentTX
  Sending raw data from the Digilent Arty FPGA board
  ☆23Updated 8 years ago
• fpga-soc / mil-std-1553b-soc
  development interface mil-std-1553b for system on chip
  ☆21Updated 7 years ago
• m-labs / lm32
  LatticeMico32 soft processor
  ☆105Updated 10 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆34Updated 7 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆59Updated last year
• enjoy-digital / liteiclink
  Small footprint and configurable Inter-Chip communication cores
  ☆57Updated last month
• PacoReinaCampo / SoC-RISCV
  System on Chip with RISCV-32 / RISCV-64 / RISCV-128
  ☆23Updated this week
• SanjayRai / PCIE_AXI_BRIDGE
  Pcie to AXI Bridge in Xilinx series-7 Kintex and Artix devices
  ☆29Updated 8 years ago
• ZipCPU / s6soc
  CMod-S6 SoC
  ☆40Updated 7 years ago
• blackmesalabs / MesaBusProtocol
  Flexible Byte transport protocol for bus bridging CPUs to FPGAs over UART,SPI,SERDES physical interfaces
  ☆32Updated 4 months ago
• imrickysu / ZYNQ-Custom-Board-Bring-Up-Guide
  This is a guide for bringing up custom ZYNQ boards. It covers test sequence, test method, common error situations and code and project th…
  ☆67Updated 7 years ago
• gtjennings1 / HyperBUS
  A basic HyperRAM controller for Lattice iCE40 Ultraplus FPGAs
  ☆61Updated 6 years ago
• cambridgehackers / fpgajtag
  A simple jtag programming tool that has been verified on a variety of Xilinx Series7 platforms.
  ☆35Updated 2 years ago
• stnolting / cjtag_bridge
  🔌 Compact JTAG ("cJTAG") to 4-wire JTAG (IEEE 1149.1) bridge.
  ☆23Updated 3 years ago
• stevenbell / csirx
  Open-source CSI-2 receiver for Xilinx UltraScale parts
  ☆37Updated 5 years ago
• chiggs / oc_jpegencode
  Fork of OpenCores jpegencode with Cocotb testbench
  ☆43Updated 9 years ago
• Galland / LEON2
  LEON2 SPARC CPU IP core LGPL by Gaisler Research
  ☆18Updated 12 years ago