IFM-Ulm / ro-pr-fw
Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
☆10Updated 4 years ago
Related projects ⓘ
Alternatives and complementary repositories for ro-pr-fw
- FPGA implementation of a physical unclonable function for authentication☆32Updated 7 years ago
- A Built-in-Self-Test Scheme for Online Evaluation of Physical Unclonable Functions and True Random Number Generators☆21Updated 7 years ago
- Defense/Attack PUF Library (DA PUF Library)☆46Updated 4 years ago
- This is a Verilog algorithm which takes 8bits and encrypts the data for the purpose of secure communication based on the concept of Ellip…☆29Updated 6 years ago
- AES hardware engine for Xilinx Zynq platform☆28Updated 3 years ago
- Hardware Implementation of Advanced Encryption Standard Algorithm in Verilog☆37Updated 7 years ago
- Implementation of cryptographic algorithm with verilog hdl(such as des,aes,sha,rsa,ecc etc.)☆35Updated 4 years ago
- Custom Coprocessor Interface for VexRiscv☆10Updated 6 years ago
- FPGA implementation of a cryptographically secure physical unclonable function based on learning parity with noise problem.☆15Updated 7 years ago
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆22Updated 2 years ago
- Implementation of ECC on FPGA-Zynq7000 SoC☆17Updated 5 years ago
- An end-to-end chip authentication architecture based on SRAM PUF and public key cryptography.☆15Updated 5 years ago
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆10Updated 4 years ago
- ☆12Updated 9 years ago
- An FPGA Implementation of Arbiter PUF with 4x4 Switch Blocks☆14Updated 4 years ago
- Reference implementation for the COherent Sampling ring Oscillator based True Random Number Generator.☆12Updated this week
- VexRiscv reference platforms for the pqriscv project☆15Updated 8 months ago
- Verilog Implementation of modular exponentiation using Montgomery multiplication☆32Updated 10 years ago
- A barebones 64-bit RISC-V micro-controller class CPU, implementing the I(nteger), M(ul/div), C(ompressed) and K(ryptography) extensions.☆43Updated 2 years ago
- CoPHEE is a Co-processor for Partially Homomorphic Encrypted Encryption.☆27Updated 9 months ago
- C++ and Verilog to implement AES128☆16Updated 6 years ago
- I present a novel pipelined fast Fourier transform (FFT) architecture which is capable of producing the output sequence in normal order. …☆37Updated 11 months ago
- Ring Oscillator Physically Unclonable Funtion☆18Updated 3 years ago
- True Random Number Generator core implemented in Verilog.☆72Updated 4 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆23Updated 2 years ago
- A list of VHDL codes implementing cryptographic algorithms☆25Updated 2 years ago
- SRAM☆20Updated 4 years ago
- RISC-V instruction set extensions for SM4 block cipher☆18Updated 4 years ago
- ☆18Updated 10 years ago
- Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and h…☆19Updated 3 years ago