Framework based on Partial Reconfiguration for chip characterization utilizing ring-oscillator PUFs
☆13Apr 1, 2020Updated 5 years ago
Alternatives and similar repositories for ro-pr-fw
Users that are interested in ro-pr-fw are comparing it to the libraries listed below
Sorting:
- FPGA implementation of a physical unclonable function for authentication☆33Apr 7, 2017Updated 8 years ago
- SDR-Transceiver☆10Dec 30, 2019Updated 6 years ago
- C++ library for AXI DMA with direct and scatter-gather support☆13Feb 22, 2022Updated 4 years ago
- Real-Time Hardware Sorter, Using A Multi-Dimensional Sorting Algorithm☆19Jan 4, 2026Updated 2 months ago
- ESP32-NOW with Wifi☆23Apr 11, 2025Updated 10 months ago
- ☆19Oct 11, 2023Updated 2 years ago
- Framework for FPGA-accelerated Middlebox Development☆49Feb 18, 2023Updated 3 years ago
- Ring Oscillator Physically Unclonable Funtion☆26Sep 9, 2021Updated 4 years ago
- A graphical user interface for measuring and performing inter-active analysis of physical unclonable functions (PUFs)☆27Jun 24, 2020Updated 5 years ago
- ARTICo³ - Dynamic and Partially Reconfigurable Architecture for Run-Time Adaptive, High Performance Embedded Computing☆12Sep 10, 2024Updated last year
- Hardware Security Labs☆31May 3, 2017Updated 8 years ago
- Triple Modular Redundancy☆30Sep 4, 2019Updated 6 years ago
- ☆26Nov 16, 2023Updated 2 years ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互，CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程： 1. 链路初始化： 在上位机完成USB固件的下载，并读取…☆29Nov 9, 2015Updated 10 years ago
- Technology-agnostic Physical Unclonable Function (PUF) hardware module for any FPGA.☆139Nov 5, 2022Updated 3 years ago
- A project demonstrate how to config ad9361 to TX mode☆11Dec 9, 2018Updated 7 years ago
- Present Crypto Engine in Verilog☆11Feb 27, 2016Updated 10 years ago
- Utilities for Avalon Memory Map☆11Jul 11, 2024Updated last year
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆12Jul 14, 2024Updated last year
- FPGA Low latency 10GBASE-R PCS☆12May 23, 2023Updated 2 years ago
- ☆10Oct 18, 2024Updated last year
- CES VHDL utility library, with packages, memories, FIFOs, Clock Domain Crossing and more useful VHDL modules☆11Jan 17, 2022Updated 4 years ago
- VHDL sources for a BT.656 to axi4-stream converter☆12Mar 20, 2023Updated 2 years ago
- OpenExSys_NoC a mesh-based network on chip IP.☆20Dec 1, 2023Updated 2 years ago
- mechatronics firmware☆13Apr 14, 2025Updated 10 months ago
- Convert Xilinx FPGA bitstream from the .bit format (as generated by Vivado) into the .bin format (as expected by Linux fpga_manager)☆14Sep 5, 2023Updated 2 years ago
- Lock circuitgraphs using various logic locking techniques☆11May 2, 2023Updated 2 years ago
- Ultra High Performance AXI4-based Direct Memory Access (DMA) Controller. This project was an interview assignment. Work in Progress.☆13Oct 19, 2024Updated last year
- Instruction and files for porting Arm DesignStart to CW305.☆16Dec 6, 2023Updated 2 years ago
- Example SystemVerilog UVM Environment☆10Jun 23, 2015Updated 10 years ago
- ☆14Jan 22, 2026Updated last month
- Python tools for processing Verilog files☆10Dec 7, 2011Updated 14 years ago
- Design of High-Level Synthesis of Xilinx FFT IP core via FFT library☆14Jul 17, 2023Updated 2 years ago
- Trying to learn Wishbone by implementing few master/slave devices☆13Jan 7, 2019Updated 7 years ago
- Hardware-backed biometric authentication for Flutter. Create cryptographic signatures using device biometrics with keys stored in Secure …☆15Updated this week
- Code repository for my articles on blogs.embarcadero.com and pythongui.org.☆13Feb 6, 2025Updated last year
- Time management library for embedded devices☆12Apr 21, 2019Updated 6 years ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- Designing and implementing LZ4 decompression algorithm in hardware (FPGA) using Verilog hardware description language☆17Feb 20, 2019Updated 7 years ago