takeshineshiro / fpga_fibre_scanLinks
本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取固件的信息状态描述后,通过上电复位或者手动复位,通过串口发送0X55给上位机,表明链路打通,一次握手成功。 2. 超声波发射与AD数据接收:在收到上位机通过串口发送的0X02指令后,开启(START),发送超声方波信号,(注:该START信号在处理过程被改变成包络信号)因为只是单阵元,所以就没有接收延迟聚焦的问题,但有皮肤表皮的客观实际和单阵元回波的时间消耗,所以在等到C_CORDIC_DELAY(1000)后,才开…
☆28Updated 9 years ago
Alternatives and similar repositories for fpga_fibre_scan
Users that are interested in fpga_fibre_scan are comparing it to the libraries listed below
Sorting:
- OscillatorIMP ecosystem FPGA IP sources☆28Updated 2 months ago
- Open source zynq platform☆18Updated 7 years ago
- 软件无线电,使用FPGA进行正交解调。☆22Updated 6 years ago
- ☆17Updated 4 years ago
- Testbenches for HDL projects☆20Updated this week
- an sata controller using smallest resource.☆16Updated 11 years ago
- minimal code to access ps DDR from PL☆20Updated 5 years ago
- SEA-S7_gesture recognition☆17Updated 5 years ago
- MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX w…☆58Updated 7 months ago
- ☆31Updated 4 years ago
- 基于arm cortex-m0内核的xillinx fpga sopc 工程项目☆13Updated 6 years ago
- 标准视频时序生成器☆10Updated 5 years ago
- Colorspace conversion, gamma correction, and more -- all integrated within a MIPI-to-HDMI pipeline in FPGA.☆30Updated 5 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆72Updated 3 years ago
- turbo 8051☆29Updated 8 years ago
- 基于USB2.0 的数据采集卡☆19Updated 6 years ago
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆12Updated 8 years ago
- Simple mono FM Radio.☆48Updated 9 years ago
- AD7606 driver verilog☆44Updated 6 years ago
- FMC card to allow interfacing Xilinx FPGA boards with Jetson TX2 or TX1 via CSI-2 camera interface☆18Updated 2 years ago
- 基于Kintex-7 XC7K325T的高性能FPGA功能验证板☆19Updated 5 years ago
- Altera Cyclone IV FPGA project for the PCIe LimeSDR board☆40Updated 2 years ago
- ☆32Updated last year
- Verilog CAN controller that is compatible to the SJA 1000.☆13Updated 4 years ago
- Register-based and RAM-based FIFOs designed in Verilog/System Verilog.☆19Updated last year
- DSP with FPGAs 3. edition ISBN: 978-3-540-72612-8☆15Updated 3 years ago
- Controller for i2c EEPROM chip in Verilog for Mojo FPGA board☆24Updated 9 years ago
- ☆29Updated 4 years ago
- ☆36Updated 5 years ago
- SPI通信实现FLASH读写☆16Updated 5 years ago