Alternatives and similar repositories for keccak-verilog

Users that are interested in keccak-verilog are comparing it to the libraries listed below

• hdl-modules / hdl-modules
  A collection of reusable, high-quality, peer-reviewed VHDL building blocks.
  ☆172Updated this week
• secworks / aes
  Verilog implementation of the symmetric block cipher AES (Advanced Encryption Standard) as specified in NIST FIPS 197. This implementatio…
  ☆371Updated 3 months ago
• daringpatil3134 / SPI_Serial_Peripheral_Interface_Verilog_Modules
  Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device
  ☆12Updated last year
• raysalemi / Python4RTLVerification
  ☆161Updated 2 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆270Updated last year
• Subhasis-Sahu / SFAL-VSD
  ☆13Updated 9 months ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆159Updated 2 months ago
• accellera-official / uvm-core
  ☆87Updated 10 months ago
• pyuvm / pyuvm
  The UVM written in Python
  ☆440Updated this week
• open-logic / open-logic
  Open Logic FPGA Standard Library
  ☆671Updated 2 weeks ago
• themperek / cocotb-test
  Unit testing for cocotb
  ☆160Updated last month
• fpganinja / taxi
  AXI, AXI stream, Ethernet, and PCIe components in System Verilog
  ☆290Updated 3 weeks ago
• lowRISC / ibex-demo-system
  A demo system for Ibex including debug support and some peripherals
  ☆73Updated last month
• amradel2020 / vlsi_linkedin_index
  This repo provide an index of VLSI content creators and their materials
  ☆152Updated 10 months ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆355Updated last year
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆572Updated 3 months ago
• Xilinx / Vivado-Design-Tutorials
  ☆213Updated last month
• lowRISC / style-guides
  lowRISC Style Guides
  ☆440Updated last month
• barbedo / vivado-git
  A git-friendly Vivado wrapper
  ☆235Updated last year
• svunit / svunit
  ☆204Updated 4 months ago
• OSVVM / OSVVM
  OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...
  ☆243Updated 3 weeks ago
• JAYRAM711 / 100-DAYS-OF-RTL
  This Repo contains Codes of RTLs for implementation of various circuit designs using Verilog in Xilinx ISE 14.7 and sometimes Modelsim to…
  ☆19Updated last year
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆492Updated 3 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆364Updated last month
• SystemRDL / PeakRDL
  Control and status register code generator toolchain
  ☆138Updated last month
• slaclab / surf
  A huge VHDL library for FPGA and digital ASIC development
  ☆391Updated this week
• mattvenn / awesome-opensource-asic-resources
  ☆333Updated 2 years ago
• fayizferosh / soc-design-and-planning-nasscom-vsd
  2 Week digital VLSI SoC design and planning workshop with complete RTL2GDSII flow organised by VSD in collaboration with NASSCOM (Advance…
  ☆25Updated last year
• harpreetbhatia / sv_practice
  Practice exercises for SystemVerilog, UVM ..
  ☆24Updated 5 years ago
• cluelogic / uvm-tutorial-for-candy-lovers
  Source code repo for UVM Tutorial for Candy Lovers
  ☆192Updated 8 years ago