A Verilog (specifically, System Verilog) implementation of the not-yet-finalized SHA-3 winner, Keccak.
☆15Apr 8, 2026Updated 7 months ago
Alternatives and similar repositories for keccak-verilog
Users that are interested in keccak-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆13Updated this week
- ☆11Oct 29, 2026Updated last week
- Verilog implementation of 1024 bit Hybrid Montgomery Multiplication/Exponentiation☆14Nov 28, 2019Updated 6 years ago
- 4096bit Iterative digit-digit Montgomery Multiplication in Verilog☆20Apr 18, 2022Updated 4 years ago
- Generates simple AXI4-lite IP for use in Vivado from register specifications☆16Oct 13, 2026Updated 3 weeks ago
- Managed Kubernetes at scale on DigitalOcean • AdDigitalOcean Kubernetes includes the control plane, bandwidth allowance, container registry, automatic updates, and more for free.
- ☆14Feb 8, 2022Updated 4 years ago
- VexRiscv reference platforms for the pqriscv project☆16Mar 9, 2024Updated 2 years ago
- ☆12Jan 13, 2022Updated 4 years ago
- A Versa Board implementation using the AutoFPGA/ZipCPU infrastructure☆17Nov 19, 2019Updated 6 years ago
- ☆19Nov 8, 2024Updated 2 years ago
- SIMON and SPECK, the two lightweight block ciphers designed by the researchers from NSA☆24Jul 12, 2013Updated 13 years ago
- Adversarial driving simulator for testing safety validation algorithms☆15Jun 13, 2021Updated 5 years ago
- FIPS 202 compliant SHA-3 core in Verilog☆26Oct 8, 2020Updated 6 years ago
- Fixed point math library for SystemVerilog☆45Nov 14, 2024Updated last year
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- AES implementations in chisel, PyRTL, VivadoHLS, C++ and Python☆11Apr 18, 2022Updated 4 years ago
- Direct Access Memory for MPSoC☆13Updated this week
- ArtyS7-50 VexRiscV LiteX SoC using multiple Ethernet Interface☆18Dec 23, 2020Updated 5 years ago
- ☆13Jun 9, 2022Updated 4 years ago
- Implementation of a Serial Peripheral Interface(SPI) using Verilog and testing various modes of the SPI Device☆23Jul 7, 2024Updated 2 years ago
- SQISign: Short Quaternion and Isogeny Signature – C implementation based on PARI/GP (obsolete implementation)☆27Feb 23, 2023Updated 3 years ago
- Datasets from CHES papers on random delays☆14Apr 13, 2021Updated 5 years ago
- SystemVerilog examples and projects☆21Jun 10, 2025Updated last year
- Situation Coverage-based AV-Testing Framework in CALRA☆14Mar 30, 2023Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- This is one of the first approaches to an LTE Simulink model that was developed in the world, back in 2013. It is based on Turbo Coding,…☆12Nov 1, 2017Updated 9 years ago
- DMA Project using Verilog HDL☆15Dec 26, 2019Updated 6 years ago
- Hardware description (VHDL) and configuration scripts (Python) of a versatile IIR Filter implemented as cascaded SOS/biquads. No vendor-s…☆20May 28, 2018Updated 8 years ago
- Belfort FPGA acceleration for TFHE-rs; for demo use on AWS☆29Mar 25, 2026Updated 7 months ago
- ☆26Feb 20, 2024Updated 2 years ago
- MASCAB: a Micro-Architectural Side-Channel Attack Bibliography☆42Oct 13, 2026Updated 3 weeks ago
- 第六期“一生一芯“计划☆10May 7, 2024Updated 2 years ago
- VSCode extension for enhancing verilog☆25Apr 27, 2024Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆18Feb 12, 2024Updated 2 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- A handwritten digit recognition painter implementation on Basys 3 Artix-7 FPGA using Verilog.☆24Oct 29, 2023Updated 3 years ago
- Secure AES128 Encryption Implementation for ATmega8515☆37Feb 15, 2021Updated 5 years ago
- ChipSeeker（本地免费版，已停止更新）☆32Sep 14, 2026Updated last month
- ☆27Aug 11, 2021Updated 5 years ago
- Implementing Different Adder Structures in Verilog☆78Sep 3, 2019Updated 7 years ago
- DMA Hardware Description with Verilog☆20Dec 20, 2019Updated 6 years ago
- ☆27Nov 2, 2017Updated 9 years ago
Are these results useful?