AntonLydike / riscemu
RISC-V emulator in python
☆51Updated 4 months ago
Related projects ⓘ
Alternatives and complementary repositories for riscemu
- ☆12Updated last week
- Testing processors with Random Instruction Generation☆29Updated last month
- Debuggable hardware generator☆67Updated last year
- Visual Simulation of Register Transfer Logic☆89Updated last year
- Lipsi: Probably the Smallest Processor in the World☆81Updated 7 months ago
- Wrappers for open source FPU hardware implementations.☆31Updated 7 months ago
- The specification for the FIRRTL language☆46Updated this week
- Lectures for the Agile Hardware Design course in Jupyter Notebooks☆79Updated 7 months ago
- CIRCT-based HLS compilation flows, debugging, and cosimulation tools.☆44Updated last year
- A GPU acceleration flow for RTL simulation with batch stimulus☆93Updated 7 months ago
- Library to compile Chisel circuits using LLVM/MLIR (CIRCT)☆70Updated last year
- NucleusRV - A 32-bit 5 staged pipelined risc-v core.☆60Updated last month
- DHLS (Dynamic High-Level Synthesis) compiler based on MLIR☆64Updated this week
- Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project☆135Updated last month
- RISC-V Core; superscalar, out-of-order, multi-core capable; based on RISCY-OOO from MIT☆161Updated 3 months ago
- high-performance RTL simulator☆140Updated 5 months ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆89Updated 3 years ago
- Dual-issue RV64IM processor for fun & learning☆57Updated last year
- ☆12Updated 3 months ago
- ☆32Updated last week
- Proposed RISC-V Composable Custom Extensions Specification☆67Updated 6 months ago
- slang-based frontend for Yosys☆43Updated this week
- A Hardware Pipeline Description Language☆40Updated last year
- A 32-bit RISC-V Processor Designed with High-Level Synthesis☆47Updated 4 years ago
- An open source high level synthesis (HLS) tool built on top of LLVM☆118Updated 5 months ago
- Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.☆75Updated this week
- RISC-V Formal Verification Framework☆111Updated last month
- Floating point modules for CHISEL☆28Updated 10 years ago
- Infrastructure to drive Spike (RISC-V ISA Simulator) in cosim mode. Hammer provides a C++ and Python interface to interact with Spike.☆24Updated last year
- A hardware synthesis framework with multi-level paradigm☆37Updated last year