Alternatives and similar repositories for riscemu

Users that are interested in riscemu are comparing it to the libraries listed below

• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆101Updated last month
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆46Updated 3 weeks ago
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆118Updated last week
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆111Updated 3 weeks ago
• Kuree / kratos
  Debuggable hardware generator
  ☆70Updated 2 years ago
• leros-dev / leros
  A Tiny Processor Core
  ☆110Updated 2 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 4 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆63Updated 2 weeks ago
• wallento / riscv-python-model
  Python Model of the RISC-V ISA
  ☆55Updated 3 years ago
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆128Updated this week
• ucb-bar / libgloss-htif
  A libgloss replacement for RISC-V that supports HTIF
  ☆38Updated last year
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆97Updated 4 months ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆102Updated last month
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆158Updated 3 years ago
• riscvarchive / riscv-CMOs
  ☆90Updated last month
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆146Updated last month
• ucsc-vama / essent
  high-performance RTL simulator
  ☆178Updated last year
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆86Updated last year
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆113Updated last year
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆150Updated last week
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆134Updated last week
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆151Updated last year
• ucb-bar / berkeley-testfloat-3
  TestFloat release 3
  ☆68Updated 6 months ago
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆25Updated 2 years ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆48Updated last year
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆75Updated this week
• bsc-loca / sargantana
  ☆108Updated last month
• pulp-platform / pulp_cluster
  The multi-core cluster of a PULP system.
  ☆108Updated last week
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆124Updated last year