Alternatives and similar repositories for riscemu:

Users that are interested in riscemu are comparing it to the libraries listed below

• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆91Updated last week
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆80Updated this week
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• gvsoc / gvsoc
  ☆14Updated this week
• pulp-platform / spatz
  Spatz is a compact RISC-V-based vector processor meant for high-performance, small computing clusters.
  ☆84Updated this week
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆49Updated last week
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆48Updated this week
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆99Updated 9 months ago
• schoeberl / lipsi
  Lipsi: Probably the Smallest Processor in the World
  ☆82Updated 9 months ago
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆69Updated 8 months ago
• sifive / chisel-circt
  Library to compile Chisel circuits using LLVM/MLIR (CIRCT)
  ☆70Updated last year
• ovh / sv2chisel
  (System)Verilog to Chisel translator
  ☆109Updated 2 years ago
• agile-hw / lectures
  Lectures for the Agile Hardware Design course in Jupyter Notebooks
  ☆82Updated 9 months ago
• CTSRD-CHERI / sail-cheri-riscv
  CHERI-RISC-V model written in Sail
  ☆56Updated last week
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆83Updated 4 months ago
• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆30Updated last week
• ucsc-vama / essent
  high-performance RTL simulator
  ☆149Updated 6 months ago
• thoughtworks / hardposit-chisel3
  Chisel library for Unum Type-III Posit Arithmetic
  ☆36Updated 9 months ago
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆95Updated last week
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆58Updated this week
• zhemao / chisel-float
  Floating point modules for CHISEL
  ☆30Updated 10 years ago
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆138Updated last month
• pku-liang / Hector
  A hardware synthesis framework with multi-level paradigm
  ☆36Updated last week
• aswaterman / trainwreck
  Original RISC-V 1.0 implementation. Not supported.
  ☆41Updated 6 years ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆55Updated 5 months ago
• wallento / riscv-python-model
  Python Model of the RISC-V ISA
  ☆49Updated 2 years ago
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆39Updated this week
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆63Updated 4 years ago
• tenstorrent / whisper
  ☆36Updated this week
• Kuree / kratos
  Debuggable hardware generator
  ☆67Updated last year