Alternatives and similar repositories for riscemu:

Users that are interested in riscemu are comparing it to the libraries listed below

• CTSRD-CHERI / TestRIG
  Testing processors with Random Instruction Generation
  ☆35Updated this week
• Kuree / kratos
  Debuggable hardware generator
  ☆68Updated 2 years ago
• dian-lun-lin / RTLflow
  A GPU acceleration flow for RTL simulation with batch stimulus
  ☆106Updated last year
• leonardt / verilogAST-cpp
  C++17 implementation of an AST for Verilog code generation
  ☆24Updated last year
• mortbopet / VSRTL
  Visual Simulation of Register Transfer Logic
  ☆96Updated last month
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆89Updated this week
• t-crest / patmos
  Patmos is a time-predictable VLIW processor, and the processor for the T-CREST project
  ☆141Updated last month
• tenstorrent / whisper
  ☆37Updated last week
• EPFL-LAP / dynamatic
  DHLS (Dynamic High-Level Synthesis) compiler based on MLIR
  ☆102Updated this week
• grayresearch / CX
  Proposed RISC-V Composable Custom Extensions Specification
  ☆70Updated 10 months ago
• riscv-software-src / riscv-isac
  ☆32Updated 5 months ago
• lac-dcc / chimera
  A tool for synthesizing Verilog programs
  ☆76Updated this week
• Kuree / hgdb
  Hardware generator debugger
  ☆73Updated last year
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆87Updated 6 months ago
• apl-cornell / PDL
  A Hardware Pipeline Description Language
  ☆43Updated last year
• rdaly525 / coreir
  ☆102Updated 2 years ago
• dillonhuff / ahaHLS
  An open source high level synthesis (HLS) tool built on top of LLVM
  ☆119Updated 9 months ago
• pulp-platform / snitch_cluster
  An energy-efficient RISC-V floating-point compute cluster.
  ☆71Updated last week
• YosysHQ / eqy
  Equivalence checking with Yosys
  ☆40Updated 3 weeks ago
• dillonhuff / clockwork
  A polyhedral compiler for hardware accelerators
  ☆56Updated 8 months ago
• wallento / riscv-python-model
  Python Model of the RISC-V ISA
  ☆50Updated 2 years ago
• chipsalliance / fpga-interchange-schema
  ☆55Updated 2 years ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆41Updated 11 months ago
• openhwgroup / core-v-xif
  RISC-V eXtension interface that provides a generalized framework suitable to implement custom coprocessors and ISA extensions
  ☆60Updated 10 months ago
• cristian-mattarei / CoSA
  CoreIR Symbolic Analyzer
  ☆70Updated 4 years ago
• chipsalliance / firrtl-spec
  The specification for the FIRRTL language
  ☆53Updated this week
• chipsalliance / systemc-compiler
  Intel Compiler for SystemC
  ☆23Updated last year
• gvsoc / gvsoc
  ☆18Updated this week
• pulp-platform / morty
  A SystemVerilog source file pickler.
  ☆56Updated 5 months ago
• ucsc-vama / essent
  high-performance RTL simulator
  ☆154Updated 9 months ago