srimanthtenneti / Hell_Fire_SoC_Demo
☆14Updated last month
Related projects ⓘ
Alternatives and complementary repositories for Hell_Fire_SoC_Demo
- ☆26Updated 7 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆16Updated last year
- ☆39Updated 2 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆34Updated 2 years ago
- ☆10Updated 4 months ago
- VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…☆13Updated 4 years ago
- ☆16Updated last year
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆34Updated 2 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆20Updated 5 months ago
- This repository contain the implementaton of RV32I 5-Stage-Pipeline-Processor based on RISC-V ISA and designed on Verilog☆10Updated 8 months ago
- APB UVC ported to Verilator☆11Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆63Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆21Updated last year
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆27Updated 2 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆12Updated 9 months ago
- tools to help make the most of the limited space we have on the Google sponsored Efabless shuttles☆35Updated last year
- ☆16Updated 2 years ago
- This repository aims to capture the works done in 5-day workshop of Adavance Physical Design using OpenLANE/SkyWater130. The workshop hel…☆22Updated 3 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆50Updated 2 years ago
- This project describes how the PNR of an analog IP, 2:1 analog multiplexer is carried out by opensource EDA tools, Openlane. It also disc…☆42Updated 3 years ago
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆37Updated 3 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆63Updated 3 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆45Updated 7 months ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆22Updated 3 years ago
- A 32 bit RISCV Based SOC with QSpi , Uart and 8 bit SDRAM Controller tagetted to efebless shuttle program☆17Updated last year
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆22Updated 2 years ago
- RTL development of Quad Serial Peripheral Interface (Quad-SPI) on QuestaSim using SystemVerilog.☆18Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆53Updated 2 weeks ago
- ☆52Updated last year
- This repository contains simulation files and other relevant files on the On-chip clock multiplier (PLL) (Fclkin—5MHz to 12MHz, Fclkout—4…☆15Updated 3 years ago