srimanthtenneti / Hell_Fire_SoC_DemoLinks
☆24Updated 8 months ago
Alternatives and similar repositories for Hell_Fire_SoC_Demo
Users that are interested in Hell_Fire_SoC_Demo are comparing it to the libraries listed below
Sorting:
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆27Updated 3 years ago
- ☆41Updated last year
- Accelerating the AES algorithm on an FPGA and comparing the speedup with both AES and Modified AES algorithms☆27Updated 3 years ago
- VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.☆43Updated 3 years ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆24Updated last year
- ☆41Updated 3 years ago
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆29Updated 3 years ago
- ☆17Updated 2 years ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆64Updated 2 years ago
- Design of 1024x32 SRAM (32Kbits) using OpenRAM and SKY130 PDKs with operating voltage of 1.8V and access time < 2.5ns☆72Updated 4 years ago
- Implementation of the pipelined RISC V processor with many useful features as fully bypassing, dynamic branch prediction, single and mult…☆14Updated last year
- ☆12Updated 3 months ago
- This repository contains all the contents studied and created during the Advanced Physical Design Workshop using OpenLANE and SKY130 PDK☆38Updated 3 years ago
- In this workshop, we will delve into the process of designing an Application Specific Integrated Circuit (ASIC) from the Register Transf…☆11Updated 10 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆66Updated last year
- Verilog RTL Design☆42Updated 3 years ago
- This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)☆12Updated 7 months ago
- 5 Day TCL begginer to advanced training workshop by VSD☆17Updated last year
- Curriculum for a university course to teach chip design using open source EDA tools☆94Updated last year
- This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…☆70Updated 4 years ago
- This repo is created to include illustrative examples on object oriented design pattern in SV☆58Updated 2 years ago
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆60Updated last year
- General Purpose AXI Direct Memory Access☆53Updated last year
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆102Updated last month
- Design and UVM-TB of RISC -V Microprocessor☆23Updated last year
- Verilog Design, Simulation & Synthesis of Digital ASIC Projects☆15Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆59Updated 8 months ago
- The Open Source Hardware Accelerator for Efficient Neural Network Inference☆46Updated last week
- Reconfigurable Computing Lab, DESE, Indian Institiute of Science☆23Updated last year
- This project is done in the course of "Advanced Physical Design using OpenLANE/Sky130" workshop by VLSI System Design Corporation. In thi…☆46Updated 4 years ago