Alternatives and similar repositories for Pynq-LicensePlateRecognition

Users that are interested in Pynq-LicensePlateRecognition are comparing it to the libraries listed below

• Shahriar-0 / Digital-Logic-Design-Lab-Experiments-S2023
  Verilog implementation of different concepts in Digital Logic Design such as OTHFSM, AFG and Accelerators
  ☆11Updated last year
• zengchenglong / interview_digital_IC
  关于数字IC的笔试面试题
  ☆13Updated 5 years ago
• Lydaidai / The-car-base-on-FPGA
  开发环境是Windows 10, Quartus。硬件开发语言是Verilog。 利用FPGA开发的智能小车，分为两个部分，控制器部分和小车部分，通过蓝牙信号进行连接。 控制部分可以通过加速度传感器检测手势，从而控制小车的前后左右。 加速度传感器还可以检测人体是否摔倒…
  ☆14Updated 6 years ago
• tianxiaogua / FPGA-Robot
  使用FPGA制作机器人，并使用python建立上位机，FPGA机器人通过控制ESP8266通过WiFi进行无线通讯，来达到上位机控制FPGA机器人的目的
  ☆25Updated 5 years ago
• yuezhao1 / ANLU_fpga
  使用国产FPGA厂商安路公司的开发板做的一款基于FPGA的智能导盲杖系统。利用百度LBS开放平台做到自主导航，与Arduino互联实现PID算法，摄像头识别红绿灯，超声波自主避障，语音识别，一键拨打紧急联系人等等
  ☆27Updated 5 years ago
• JacoboJin / RISCV-on-PYNQ-Z2
  This repo is to inplemente the riscv soc on the xilinx pynq-z2 board
  ☆11Updated last year
• tharunchitipolu / sobel-edge-detector
  Sobel is first order or gradient based edge operator for images and it is implemented using verilog.
  ☆14Updated 4 years ago
• markos-stefanidis / FPGA-Based-HDR-algorithm
  Hardware implementation of HDR image producing algorithm
  ☆16Updated 3 years ago
• LaErre9 / Zynq_Ultrascale_Vitis_AI_CNN_ZCU102
  Workflow for Executing CNN Networks on Zynq Ultrascale+ with VITIS AI. Detailed analysis, configuration, and execution of Convolutional N…
  ☆17Updated last year
• sazczmh / PYNQ_Workshop
  ☆38Updated 6 years ago
• JF-Tan / Takk_Zynq_Labs
  This is just for Takk_Zynq_Labs test.
  ☆26Updated 3 years ago
• deepaktabraham / FPGA-Acceleration-of-Canny-Edge-Detection-Algorithm
  HW and SW based implementation of Canny Edge Detection Algorithm.
  ☆12Updated 7 years ago
• programer-guan / digital_ic_verification
  数字IC验证案例（SV and UVM）
  ☆26Updated 4 years ago
• xbdxwyh / yolov3_fpga_project
  ☆55Updated 2 years ago
• JasonCarter92 / 16QAM-Transmitter-Reciever
  DSP University Project - Matlab, Simulations, and Verilog Files
  ☆12Updated 5 years ago
• xddcore / OpenNNA
  一个开源的FPGA神经网络加速器。
  ☆180Updated 2 years ago
• Starrynightzyq / ZYNQ-PYNQ-Z2-Gobang
  2018第二届全国大学生FPGA创新设计邀请赛的作品
  ☆63Updated 6 years ago
• vitaliikulin / I2C-FPGA-Verilog-HDL
  In this project, I am developing an I2C interface (IIC, TWI) for the FPGA platform. In this project I use the Verilog HDL digital hardwar…
  ☆19Updated 5 years ago
• markcxli / FPGA_DPU
  This project is to implement YOLO v3 on Xilinx FPGA with DPU
  ☆63Updated 5 years ago
• ahegazy / vlsi-notes
  Digital IC design and vlsi notes
  ☆12Updated 5 years ago
• AugustinJose1221 / FPGA-Build
  A novel architectural design for stitching video streams in real-time on an FPGA.
  ☆131Updated 3 years ago
• 19801201 / SpinalHDL_CNN_Accelerator
  CNN accelerator implemented with Spinal HDL
  ☆152Updated last year
• charley871103 / TPU
  AI Chip project
  ☆32Updated 4 years ago
• DexWen / LMS-Adaptive-filter
  LMS-Adaptive Filter implement using verilog and Matlab
  ☆47Updated 8 years ago
• LukiBa / zybo_yolo
  YOLO example implementation using Intuitus CNN accelerator on ZYBO ZYNQ-7000 FPGA board
  ☆21Updated 4 years ago
• Y5Whe2D9psemu / Multi-view-Convolutional-Neural-Networks-for-3D-Shape-Recognition
  本文提出了一种基于多视图卷积神经网络的三维物体识别算法，以实现三维物体的准确识别。首先实现一个标准的卷积神经网络架构，该架构经过训练可以独立地识别形状的渲染视图，以实现即使从单一视图中也可以识别出一个三维形状。随后使用该三维物体多个角度的二维视图通过卷积神经网络识别的结果进…
  ☆11Updated 3 years ago
• xilinxfairchild / FPGABasedHighPerformanceTargetChecking
  it is a set for all the respository of the project.
  ☆98Updated 6 years ago
• zhutmost / edgeboard
  Make Baidu EdgeBoard Lite as a general Zynq FPGA development board
  ☆28Updated 2 years ago
• ayzk / Simulator_CPU
  Pipeline CPU of MIPS architecture with L1 Data Cache by Verilog
  ☆20Updated 4 years ago
• tastynoob / FPGA_network
  ☆37Updated 4 years ago