ilyajob05 / verilog_modulesLinks
verilog modules
☆13Updated 5 years ago
Alternatives and similar repositories for verilog_modules
Users that are interested in verilog_modules are comparing it to the libraries listed below
Sorting:
- A simple DDR3 memory controller☆57Updated 2 years ago
- SPI-Flash XIP Interface (Verilog)☆39Updated 3 years ago
- IP operations in verilog (simulation and implementation on ice40)☆56Updated 5 years ago
- Open-source high performance AXI4-based HyperRAM memory controller☆75Updated 2 years ago
- IEEE P1735 decryptor for VHDL☆35Updated 10 years ago
- UART 16550 core☆37Updated 11 years ago
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆79Updated last year
- IP Cores that can be used within Vivado☆26Updated 4 years ago
- Basic Peripheral SoC (SPI, GPIO, Timer, UART)☆64Updated 5 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆58Updated last year
- ☆59Updated 3 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆28Updated 2 years ago
- Simple 8-bit UART realization on Verilog HDL.☆107Updated last year
- An SPI to AXI4-lite bridge for easy interfacing of airhdl register banks with any microcontroller.☆49Updated last year
- UART -> AXI Bridge☆61Updated 4 years ago
- A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs☆74Updated 2 years ago
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- Extensible FPGA control platform☆62Updated 2 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 5 years ago
- Hamming ECC Encoder and Decoder to protect memories☆33Updated 5 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆84Updated 2 years ago
- Example design for the Ethernet FMC using 4 AXI Ethernet Subsystem IP blocks☆66Updated 2 months ago
- USB -> AXI Debug Bridge☆39Updated 4 years ago
- Computational Storage Device based on the open source project OpenSSD.☆26Updated 4 years ago
- Two Verilog SPI module implementations (hard and soft) with advanced options and AXI Full Interface☆22Updated 7 years ago
- A collection of phase locked loop (PLL) related projects☆106Updated last year
- ☆69Updated 3 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆91Updated 5 years ago
- Open source FPGA-based NIC and platform for in-network compute☆66Updated 8 months ago
- Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application☆55Updated last week