DOUDIU / Video-Stitching-on-FPGALinks
This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface. The interface can be easily switched to the DDR3/4 located on either the PS or PL side using HP/GP ports or MIG IP.
☆13Updated 7 months ago
Alternatives and similar repositories for Video-Stitching-on-FPGA
Users that are interested in Video-Stitching-on-FPGA are comparing it to the libraries listed below
Sorting:
- This project aims to integrate image acquisition with AI acceleration to achieve functions such as multi-channel video source input captu…☆15Updated last year
- kintex7 ov13850 fpga mipi camera☆18Updated last year
- Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA☆32Updated 4 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆66Updated 3 years ago
- RTL implementation of TFlite FPGA accelerator and RISC-V controller. 3D Object Detection based on LiDAR Point Clouds.☆12Updated 2 years ago
- DSP University Project - Matlab, Simulations, and Verilog Files☆11Updated 5 years ago
- This project is designed to delay the output of the video stream in AXI-STREAM format.☆11Updated 10 months ago
- 七路图像在FPGA中实现拼接,代码会不断添加进来。☆24Updated 3 years ago
- FPGA Camera Parallel & MIPI Verilog☆21Updated 3 months ago
- Verilog implementation of a ultrasonic radar☆15Updated 7 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆55Updated 11 months ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆36Updated 3 years ago
- FPGA纯逻辑实现modbus通信☆18Updated 2 years ago
- An AXI DDR3 SDRAM controller for FPGA☆36Updated last year
- SPI interface connect to APB BUS with Verilog HDL☆32Updated 3 years ago
- 本项目为2023年全国大学生嵌入式芯片与系统设计竞赛——FPGA创新设计竞赛(高云赛道)项目,题目基于高云FPGA的多路网络视频监控编码系统。☆47Updated last year
- ISP☆11Updated last year
- The Final Project of team 8, NTUEE, Digital Circuits Lab (2021 Fall)☆32Updated 3 years ago
- USB2.0 Verilog☆17Updated 6 years ago
- An FPGA-based LZMA compressor for generic data compression. 基于FPGA的LZMA压缩器,用于通用数据压缩。☆84Updated last year
- A RTL-based project in Verilog that shows real-time video captured by a CMOS camera OV7670 and displayed on a monitor through VGA at 640 …☆17Updated 2 years ago
- 基于FPGA的图像处理模块(出自于crazybingo)(将部分IP换为纯Verilog用于跨平台移植)☆48Updated 5 years ago
- Implementation of tappped delay line TDC on FPGA☆12Updated 2 years ago
- 基于FPGA的FFT☆17Updated 6 years ago
- Delta-sigma ADC,PDM audio FPGA Implementation☆70Updated 2 years ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆54Updated 3 years ago
- 16QAM modulation and demodulation by Verilog☆20Updated 4 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆20Updated 6 years ago
- 【例程】国产高云FPGA 开发板及其工程☆28Updated 8 months ago
- 软件无线电,使用FPGA进行正交解调。☆22Updated 6 years ago