This open-source repository aims to stitch several separate video streams into a single video using DDR3/4 storage via the AXI interface. The interface can be easily switched to the DDR3/4 located on either the PS or PL side using HP/GP ports or MIG IP.
☆21Oct 28, 2024Updated last year
Alternatives and similar repositories for Video-Stitching-on-FPGA
Users that are interested in Video-Stitching-on-FPGA are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- This project aims to integrate image acquisition with AI acceleration to achieve functions such as multi-channel video source input captu…☆18Aug 25, 2023Updated 2 years ago
- ☆31Jan 23, 2021Updated 5 years ago
- Cryptography accelerator ASIC (for AES128/AES256 and SHA256) using Skywater 130nm process node (main project repo). Taped out in December…☆24Jan 13, 2021Updated 5 years ago
- FPGA纯逻辑实现modbus通信☆24Sep 5, 2022Updated 3 years ago
- Verilog implementation of a ultrasonic radar☆19Jan 7, 2018Updated 8 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- ☆14Jun 28, 2022Updated 3 years ago
- TFT Clock by Gowin FPGA | 华中科技大学 电信学院硬件课设基于国产高云FPGA的多功能TFT屏数字钟☆10Jun 14, 2023Updated 2 years ago
- AXI-4 RAM Tester Component☆21Aug 5, 2020Updated 5 years ago
- ☆14Aug 23, 2023Updated 2 years ago
- An oscilloscope written for the Mojo V3, a Spartan-6 based FPGA☆11May 23, 2017Updated 9 years ago
- IPASS -- Image Processing Algorithm Simulation Software☆11Jul 25, 2025Updated 10 months ago
- 基于ov5640摄像头的实时显示☆16Jul 29, 2022Updated 3 years ago
- Integration of SIFT and LES Algorithms☆14May 6, 2024Updated 2 years ago
- Memory Compiler Tutorial☆14Oct 7, 2020Updated 5 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- UESTC-雷达信号产生与处理的设计与验证☆19Jun 6, 2019Updated 6 years ago
- fpga for utrasound mobile device☆13Aug 10, 2015Updated 10 years ago
- The Canny Edge Detection algorithm is implemented on an FPGA using only Verilog code and no Intellectual Property, making it convenient t…☆48Apr 22, 2024Updated 2 years ago
- servo motor control with FPGA☆10Nov 14, 2015Updated 10 years ago
- OV5640摄像头驱动及TFT屏幕显示☆18Mar 13, 2019Updated 7 years ago
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆13Jul 18, 2017Updated 8 years ago
- implementation in verilog rtl for an FPGA to detect the presence of a face in an image☆12Mar 12, 2021Updated 5 years ago
- FT2232HL JTAG & UART Downloader☆22Jul 18, 2021Updated 4 years ago
- Nexys 4 DDR Artix-7☆11Jun 15, 2018Updated 7 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- High-performance FPGA-based JPEG codec accelerator☆13Dec 1, 2018Updated 7 years ago
- Bilinear interpolation realizes image scaling based on FPGA☆33Jul 11, 2020Updated 5 years ago
- 雷达信号分选任务是对雷达脉冲序列进行K-means聚类，以判定每个脉冲的所属雷达 1、对 2GHz 以内的信号进行多项滤波，以确定信号的中心频带 2、构建分选数据集，对场景中雷达脉冲序列信号进行仿真，并通过UDP传至开发处理 3、基于C++实现K-means算法并部署…☆21Aug 17, 2023Updated 2 years ago
- ☆90Apr 10, 2026Updated last month
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- Physics-Informed Neural Networks for Cardiovascular Blood Flow Simulations☆20Apr 7, 2025Updated last year
- SEA-S7_gesture recognition☆17Aug 1, 2020Updated 5 years ago
- OV7670 (Verilog HDL)Drive for FPGA☆19Mar 4, 2019Updated 7 years ago
- https://en.wikipedia.org/wiki/CAN_bus☆17Nov 6, 2020Updated 5 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- This project presents a novel approach for J peak detection in Heart-Rate monitoring. The proposed approach employs accelerometers to col…☆10Oct 30, 2023Updated 2 years ago
- DeviceIO是一个驱动框架，用于封装嵌入式HAL驱动，为上层应用提供服务。☆10Jun 1, 2024Updated last year
- Verilog design files and Icestudio file for Sobel Edge Detection with OV7670 camera using ULX3S FPGA Board☆18Nov 17, 2021Updated 4 years ago
- ☆10Feb 16, 2025Updated last year
- NeuroRVQ: Multi-Scale Biosignal Tokenization for Generative Foundation Models☆44Updated this week
- The Final Project of team 8, NTUEE, Digital Circuits Lab (2021 Fall)☆38Feb 26, 2022Updated 4 years ago
- HDMI with Verilog and an FPGA.☆20Sep 12, 2023Updated 2 years ago