Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
☆63Oct 20, 2022Updated 3 years ago
Alternatives and similar repositories for ADC-lvds
Users that are interested in ADC-lvds are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- An Verilog implementation of 7-to-1 LVDS Serializer. Which can be used for comunicating FPGAs with LVDS TFT Screens.☆51Nov 23, 2013Updated 12 years ago
- fpga for utrasound mobile device☆13Aug 10, 2015Updated 10 years ago
- Creation of a AXI Master and Yocto device driver for Zynq, using High Level Synthesis (HLS) techniques.☆13May 28, 2015Updated 10 years ago
- digital recognition base on FPGA☆12Nov 10, 2019Updated 6 years ago
- Must-have verilog systemverilog modules☆38May 1, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- ADC configurator to 7-series Xilinx FPGA (has parameters: NCHAN, SERDES MODE, SDR/DDR, DATA WIDTH, DEPTH and so on)☆13Aug 29, 2018Updated 7 years ago
- ☆36Aug 19, 2020Updated 5 years ago
- Design, fabrication, and assembly files for CMOS imaging sensor PCB☆15Mar 16, 2017Updated 9 years ago
- SEA-S7_gesture recognition☆17Aug 1, 2020Updated 5 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆30Dec 1, 2016Updated 9 years ago
- Verilog module to transmit/receive to/from RGMII compatible ethernet PHY☆31Dec 31, 2022Updated 3 years ago
- ☆46Apr 11, 2017Updated 9 years ago
- User Space NVMe Driver (modified for use on Zynq UltraScale+ MPSoC)☆11Sep 26, 2018Updated 7 years ago
- 10_100_1000 Mbps tri-mode ethernet MAC☆10Jul 17, 2014Updated 11 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- ☆30Jul 9, 2025Updated 9 months ago
- CMU 18545 FPGA project -- Multi-channel ultrasound data acquisition and beamforming system.☆83Apr 27, 2016Updated 9 years ago
- 基于USB2.0 的数据采集卡☆21Feb 20, 2019Updated 7 years ago
- MIPI CSI-2 Camera Sensor Receiver V2 Verilog HDL implementation For any generic FPGA. Tested with IMX219 IMX477 on Lattice Crosslink NX w…☆66Feb 13, 2025Updated last year
- include hdlc (miao), 422 grapher, 1553b☆21Oct 10, 2019Updated 6 years ago
- Xilinx IP repository☆13May 5, 2018Updated 7 years ago
- An oscilloscope written for the Mojo V3, a Spartan-6 based FPGA☆11May 23, 2017Updated 8 years ago
- FT2232HL JTAG & UART Downloader☆20Jul 18, 2021Updated 4 years ago
- Ethernet MAC 10/100 Mbps☆85Oct 2, 2019Updated 6 years ago
- Serverless GPU API endpoints on Runpod - Bonus Credits • AdSkip the infrastructure headaches. Auto-scaling, pay-as-you-go, no-ops approach lets you focus on innovating your application.
- DVI to LVDS Verilog converter☆25Sep 3, 2016Updated 9 years ago
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆80Mar 14, 2026Updated last month
- 上位机软件与下位机FPGA采集卡实现UDP通信,接收发送的正弦波信号帧,并保存到本地文件☆14Apr 27, 2022Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆42Jun 22, 2021Updated 4 years ago
- 🎒 Carrier board for a 6 mm C-Series MicroFC-60035 silicon photomultiplier.☆22Dec 27, 2025Updated 3 months ago
- Ethernet 10GE MAC☆46Jul 17, 2014Updated 11 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆33Nov 6, 2018Updated 7 years ago
- A simple PDM microphone interface on FPGA☆14Jan 16, 2022Updated 4 years ago
- RMII interface ethernet MAC Core for 10/100 MBit ethernet implementation with support CDC and AXI-Stream BUS without management and witho…☆14Jan 21, 2022Updated 4 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Verilog Code and Logisim simulation of a Weighted Round Robit Arbiter circuit using digital components☆20Mar 10, 2018Updated 8 years ago
- 本信号处理板主要由FPGA芯片和CYUSB3.0 芯片组成,其中FPGA模块主要完成与相关外设的交互,CYUSB3.0主要完成协议数据的传输。 2.2.1 FPGA模块 处理流程: 1. 链路初始化: 在上位机完成USB固件的下载,并读取…☆31Nov 9, 2015Updated 10 years ago
- MT29F128G based NAND flash controller☆10Jun 17, 2021Updated 4 years ago
- https://en.wikipedia.org/wiki/CAN_bus☆17Nov 6, 2020Updated 5 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆59Jun 23, 2021Updated 4 years ago
- a hardware task scheduler design☆10Sep 14, 2022Updated 3 years ago
- DC-SCM LTPI Reference Implementation☆19Jan 13, 2026Updated 3 months ago