cjhonlyone / ADC-lvdsLinks
Xilinx FPGA, ADC344X, AD9252, 14x 12x Serdes, LVDS
☆59Updated 3 years ago
Alternatives and similar repositories for ADC-lvds
Users that are interested in ADC-lvds are comparing it to the libraries listed below
Sorting:
- Delta-sigma ADC,PDM audio FPGA Implementation☆73Updated 3 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- FPGA Technology Exchange Group相关文件管理☆54Updated last month
- ☆31Updated 6 years ago
- Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP☆53Updated 4 years ago
- A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC☆67Updated 4 years ago
- DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3☆69Updated 3 weeks ago
- This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…☆61Updated 3 years ago
- Implementation of JESD204B Transport Layer & part of Data Link Layer☆39Updated 4 years ago
- SPI-Flash XIP Interface (Verilog)☆46Updated 4 years ago
- FPGA和USB3.0桥片实现USB3.0通信☆77Updated 4 years ago
- - Use FPGA to implement MIPI interface; - Get command from PC through USB communication; - Decode command in FPGA☆12Updated 8 years ago
- Interface Protocol in Verilog☆50Updated 6 years ago
- Ethernet MAC 10/100 Mbps☆84Updated 6 years ago
- 【例程】国产高云FPGA 开发板及其工程☆39Updated last year
- Gigabit Ethernet UDP communication driver☆80Updated 6 years ago
- 这是使用FPGA开发CMOS的两个真实项目,之前的fpga_design仅是一个未完善的版本,同时也删除了一些与项目无关的东西☆36Updated 8 years ago
- configurable cordic core in verilog☆53Updated 11 years ago
- 基于FPGA的FFT☆19Updated 6 years ago
- USB 2.0 Device IP Core☆72Updated 8 years ago
- MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计☆22Updated 2 years ago
- A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs☆66Updated 10 years ago
- Must-have verilog systemverilog modules☆37Updated 3 years ago
- AD7606 driver verilog☆44Updated 6 years ago
- A simple Verilog SPI master / slave implementation featuring all 4 modes.☆70Updated 4 years ago
- VHDL code for using Xilnx LVDS lines for MIPI CSI-2 TX protocol. For educational purposes☆76Updated 2 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆22Updated 7 years ago
- Testbenches for HDL projects☆22Updated last week
- FPGA纯逻辑实现modbus通信☆22Updated 3 years ago
- FPGA code for reading Hamamatsu C9100 data over cameralink using SPEXI FPGA card.☆22Updated 10 years ago