Alternatives and similar repositories for ADC-lvds:

Users that are interested in ADC-lvds are comparing it to the libraries listed below

• aquaxis / aq_mipi_csi2rx_ultrascaleplus
  ☆28Updated 5 years ago
• Hamid-R-Tanhaei / ZYNQ_ADC_DMA_LWIP
  Interfacing ZYNQ SoC device with ADC, Transferring data through DMA and LwIP
  ☆42Updated 3 years ago
• Anthon1e / JESD204B-Transport-and-Data-Link-Layer
  Implementation of JESD204B Transport Layer & part of Data Link Layer
  ☆31Updated 3 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆67Updated 2 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• suisuisi / FPGATechnologyGroup
  FPGA Technology Exchange Group相关文件管理
  ☆43Updated last year
• JefferyLi0903 / MMC
  MMC小组开发的一个基于Cortex-M0的ARM处理器核的无线SOC设计
  ☆21Updated last year
• suisuisi / FPGAandUSB3.0
  FPGA和USB3.0桥片实现USB3.0通信
  ☆60Updated 3 years ago
• RuiMachado39 / TDC
  Verilog implementation of a tapped delay line TDC
  ☆38Updated 6 years ago
• csus-senior-design / i2c
  I2C Master and Slave
  ☆32Updated 9 years ago
• hkhajanchi / fpga-pid
  Verilog Modules for a Digital PI Controller implemented on a Digilent NEXYS 4-DDR FPGA
  ☆30Updated 4 years ago
• GOOD-Stuff / srio_test
  Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)
  ☆17Updated 7 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆36Updated 3 years ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆59Updated 7 years ago
• halftop / Interface-Protocol-in-Verilog
  Interface Protocol in Verilog
  ☆49Updated 5 years ago
• alknvl / axis_udp
  This repository contains simple implementation of UDP/IP stack with 64-bit AXI-Stream interface. ICMP and ARP requests are partially supp…
  ☆47Updated 2 years ago
• suisuisi / basic_systemverilog
  Must-have verilog systemverilog modules
  ☆30Updated 2 years ago
• Frogwells / fpga_cmos_design
  这是使用FPGA开发CMOS的两个真实项目，之前的fpga_design仅是一个未完善的版本，同时也删除了一些与项目无关的东西
  ☆33Updated 7 years ago
• lisliyongming / JESD204B
  通过调试ADRV9009和AD9371对jesd204b知识点作进一步学习和总结
  ☆22Updated 5 years ago
• uwemeyerbaese / DSP_with_FPGAs_ed4
  DSP with FPGAs 4. edition ISBN: 978-3-642-45308-3
  ☆52Updated 2 years ago
• maxs-well / Ethernet-design-verilog
  Gigabit Ethernet UDP communication driver
  ☆72Updated 5 years ago
• madamic / zynq_tdc
  A fast high-resolution time-to-digital converter in the Red Pitaya Zynq-7010 SoC
  ☆55Updated 3 years ago
• CoreyChen922 / sata3_host_controller
  It is SATA 3 host controller. Using this you can read write to sata3 sdd/hdd from your fpga logic with simple memory like interface.
  ☆68Updated 8 months ago
• shun6-6 / Tri_Eth_UDP_pro_stack
  基于FPGA的三速以太网UDP协议栈设计
  ☆22Updated 10 months ago
• jobisoft / jTDC
  FPGA based 30ps RMS TDCs
  ☆82Updated 6 years ago
• DexWen / FFT_Verilog
  FFT implement by verilog_测试验证已通过
  ☆53Updated 8 years ago
• m-labs / tdc-core
  A 26ps RMS time-to-digital converter (TDC) core for Spartan-6 FPGAs
  ☆59Updated 10 years ago
• WayneGong / Image_Rotate
  视频旋转（2019FPGA大赛）
  ☆31Updated 4 years ago
• freecores / mac_layer_switch
  100 MB/s Ethernet MAC Layer Switch
  ☆14Updated 10 years ago
• janschiefer / verilog_spi
  A simple Verilog SPI master / slave implementation featuring all 4 modes.
  ☆50Updated 4 years ago