0BAB1 / python_to_fpga_course
A course based on FINN with hands on Lectures, Examples and Labs to go from 0 to a full custom Quantized Neural Network running on your very own FPGA !
☆14Updated 3 weeks ago
Related projects ⓘ
Alternatives and complementary repositories for python_to_fpga_course
- Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.☆27Updated this week
- PolyLUT is the first quantized neural network training methodology that maps a neuron to a LUT while using multivariate polynomial functi…☆39Updated 9 months ago
- ☆82Updated 5 months ago
- Quantized ResNet50 Dataflow Acceleration on Alveo, with PYNQ☆51Updated 2 years ago
- Vitis HLS Library for FINN☆180Updated 2 weeks ago
- CHARM: Composing Heterogeneous Accelerators on Versal ACAP Architecture☆123Updated this week
- Residual Binarized Neural Network☆44Updated 6 years ago
- Open Source Compiler Framework using ONNX as Frontend and IR☆29Updated 2 years ago
- ☆55Updated 4 years ago
- Simple examples for FPGA design using Vivado HLS for high level synthesis and Vivado for bitstream generation.☆25Updated 4 years ago
- An Open Workflow to Build Custom SoCs and run Deep Models at the Edge☆64Updated 3 months ago
- Dataflow QNN inference accelerator examples on FPGAs☆183Updated last week
- ☆69Updated last year
- ☆104Updated 5 years ago
- A collection of tutorials for the fpgaConvNet framework.☆30Updated last month
- HLS implemented systolic array structure☆40Updated 7 years ago
- PYNQ-Torch: a framework to develop PyTorch accelerators on the PYNQ platform☆66Updated 4 years ago
- ☆24Updated this week
- Repository for work on on Xilinx's matrix vector activation unit's RTL implementation. Documentation available at: https://asadalam.githu…☆15Updated 2 years ago
- Library of approximate arithmetic circuits☆49Updated 2 years ago
- Convolutional Neural Network Using High Level Synthesis☆83Updated 4 years ago
- A SystemVerilog implementation of Row-Stationary dataflow and Hierarchical Mesh Network-on-Chip Architecture based on Eyeriss CNN Acceler…☆129Updated 4 years ago
- ☆69Updated 4 years ago
- An LSTM template and a few examples using Vivado HLS☆42Updated 6 months ago
- A DSL for Systolic Arrays☆78Updated 5 years ago
- RTL implementation of Flex-DPE.☆90Updated 4 years ago
- Hardware accelerator for convolutional neural networks☆26Updated 2 years ago
- ☆93Updated 4 years ago
- FracBNN: Accurate and FPGA-Efficient Binary Neural Networks with Fractional Activations☆87Updated 3 years ago
- PYNQ Composabe Overlays☆67Updated 4 months ago