zhangly / azpr_cpu
用Altera FPGA芯片自制CPU
☆41Updated 10 years ago
Alternatives and similar repositories for azpr_cpu:
Users that are interested in azpr_cpu are comparing it to the libraries listed below
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆82Updated 4 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆69Updated 3 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆28Updated last year
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆31Updated 5 years ago
- A MCU implementation based PODES-M0O☆18Updated 5 years ago
- 根据最近看的一本书编写的对应RTL以及Testbench☆19Updated 8 years ago
- A series of RISC-V soft core processor written from scratch. Now, we're using all open-source toolchain (chisel, mill, verilator, NEMU, …☆38Updated last year
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆23Updated 8 years ago
- An embed RISC-V Core with RV32IMZicsr ISA named SparrowRV.☆62Updated 2 years ago
- SPI通信实现FLASH读写☆13Updated 5 years ago
- 软件无线电,使用FPGA进行正交解调。☆20Updated 6 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆103Updated 2 years ago
- FPGAandLAN☆25Updated 3 years ago
- SPI-Flash XIP Interface (Verilog)☆37Updated 3 years ago
- An FPGA-based HDMI display controller. 基于FPGA的HDMI显示控制器☆52Updated 9 months ago
- Extremely basic CortexM0 SoC based on ARM DesignStart Eval☆26Updated 6 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆37Updated 3 years ago
- a 4-pipeline riscv soc ( included core, periph), based with rv32im ,designed by verilog☆23Updated last year
- PulseRain Reindeer - RISCV RV32I[M] Soft CPU☆125Updated 5 years ago
- Async-Karin is an asynchronous framework for FPGA written in Verilog. It has been tested on a Xilinx Artix-7 board and an Altera Cyclone-…☆30Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆21Updated 5 years ago
- systemc建模相关☆27Updated 10 years ago
- 基于Xilinx Zynq 嵌入式软硬件协同设计实战指南☆83Updated 9 years ago
- 8051 core☆103Updated 10 years ago
- FPGA Technology Exchange Group相关文件管理☆44Updated last week
- turbo 8051☆29Updated 7 years ago
- A small SoC with a pipeline 32-bit RISC-V CPU.☆63Updated 2 years ago
- ☆18Updated 4 years ago
- 常用Verilog模块☆20Updated 5 years ago
- 这是使用FPGA开发CMOS的两个真实项目,之前的fpga_design仅是一个未完善的版本,同时也删除了一些与项目无关的东西☆33Updated 7 years ago