zhangly / azpr_cpuLinks
用Altera FPGA芯片自制CPU
☆43Updated 11 years ago
Alternatives and similar repositories for azpr_cpu
Users that are interested in azpr_cpu are comparing it to the libraries listed below
Sorting:
- OV7670 (Verilog HDL)Drive for FPGA☆18Updated 6 years ago
- 根据最近看的一本书编写的对应RTL以及Testbench☆20Updated 8 years ago
- A small test SoC for various soft-CPUs (Cortex-M0, RISC-V)☆34Updated 5 years ago
- 软件无线电,使用FPGA进行正交解调。☆23Updated 6 years ago
- 8051 core☆112Updated 11 years ago
- zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this pro…☆39Updated 4 years ago
- A VerilogHDL MCU Core based ARMv6 Cortex-M0☆22Updated 6 years ago
- ☆34Updated 4 years ago
- The next generation integrated development environment for processor design and verification. It has multi-hardware language support, o…☆113Updated 3 years ago
- A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz☆78Updated 4 years ago
- This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…☆91Updated 5 years ago
- Verilog Code for a JPEG Decoder☆34Updated 7 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 6 years ago
- systemc建模相关☆28Updated 11 years ago
- 平头哥无剑100开源SoC平台(双核E902,安全启动,BootROM,IOPMP,Mailbox,RSA-2048,SHA-2, WS2812,Flash)☆22Updated 2 years ago
- 多核处理器 ;ring network , four core, shared space memory ,directory-based cache coherency☆26Updated 9 years ago
- DMA core compatible with AHB3-Lite☆10Updated 6 years ago
- turbo 8051☆29Updated 8 years ago
- Build an open source, extremely simple DMA.☆23Updated 6 years ago
- A 32-bit RISC-V SoC on FPGA that supports RT-Thread.☆29Updated 2 years ago
- SPI通信实现FLASH读写☆16Updated 5 years ago
- A MCU implementation based PODES-M0O☆19Updated 6 years ago
- DDR3 SDRAM Memory Controller Design & Synthesis using System Verilog☆32Updated 7 years ago
- USB 2.0 Device IP Core☆74Updated 8 years ago
- 基于FPGA的FFT☆19Updated 6 years ago
- 学习AXI接口,以及xilinx DDR3 IP使用☆40Updated 8 years ago
- Quad SPI Flash XIP Controller with a direct mapped cache☆12Updated 5 years ago
- ☆30Updated 10 months ago
- 基于arm cortex-m0内核的xillinx fpga sopc工程项目☆13Updated 6 years ago
- ☆16Updated 6 years ago