yuguen / hint
High-level synthesis Integer library
☆9Updated 3 years ago
Alternatives and similar repositories for hint:
Users that are interested in hint are comparing it to the libraries listed below
- FPGA acceleration of arbitrary precision floating point computations.☆38Updated 2 years ago
- Benchmarks, testbenches, and transformed codes for high-level synthesis research☆13Updated 7 years ago
- ☆27Updated 5 years ago
- An open source PDK using TIGFET 10nm devices.☆48Updated 2 years ago
- Integration test for entire CGRA flow☆12Updated 5 years ago
- Chisel library for Unum Type-III Posit Arithmetic☆37Updated 11 months ago
- TAPA is a dataflow HLS framework that features fast compilation, expressive programming model and generates high-frequency FPGA accelerat…☆19Updated 6 months ago
- Tutorial for integrating PyMTL and Vivado HLS☆18Updated 8 years ago
- Hardware Accelerators (HwAs) constructed in Vivado HLS☆19Updated 7 years ago
- This is a hardware implementation of exact multiply accumulator for 32-bit posit number with es=2☆16Updated 7 years ago
- SForum 2020 : "A Run-time Hardware Routing Implementation for CGRA Overlays" code and data.☆11Updated 4 years ago
- LibreSilicon's Standard Cell Library Generator☆18Updated 10 months ago
- A configurable SRAM generator☆47Updated 2 months ago
- Rapidly deploy Chisel and Vivado HLS accelerators on Xilinx PYNQ☆33Updated 6 years ago
- A configurable general purpose graphics processing unit for☆11Updated 5 years ago
- Benchmarks for Yosys development☆23Updated 5 years ago
- The PE for the second generation CGRA (garnet).☆17Updated this week
- CHIPKIT: An agile, reusable open-source framework for rapid test chip development☆41Updated 4 years ago
- Business Rule Engine Hardware Accelerator☆13Updated 4 years ago
- A RISC-V processor written in BSV, based on the Flute core. Has support for integrating tightly-coupled accelerators, and for integrating…☆23Updated 2 years ago
- Project aimed at implementing floating point operators using the DSP48E1 slice.☆27Updated 11 years ago
- Streaming Message Interface: High-Performance Distributed Memory Programming on Reconfigurable Hardware☆16Updated 3 years ago
- ☆12Updated 4 years ago
- Posit Arithmetic Cores generated with FloPoCo☆24Updated 8 months ago
- Open-Source Posit RISC-V Core with Quire Capability☆55Updated last month
- Open Source PHY v2☆26Updated 10 months ago
- Lake is a framework for generating synthesizable memory modules from a high-level behavioral specification and widely-available memory ma…☆21Updated last week
- ☆22Updated 8 years ago
- TensorCore Vector Processor for Deep Learning - Google Summer of Code Project☆22Updated 3 years ago