betrusted-io / betrusted-ec
Betrusted embedded controller (UP5K)
☆45Updated last year
Alternatives and similar repositories for betrusted-ec:
Users that are interested in betrusted-ec are comparing it to the libraries listed below
- Experiments with self-synchronizing LFSR scramblers☆15Updated 4 years ago
- Experiments with Yosys cxxrtl backend☆48Updated 3 months ago
- Glacial - microcoded RISC-V core designed for low FPGA resource utilization☆84Updated 5 years ago
- Unofficial Yosys WebAssembly packages☆70Updated this week
- Hot Reconfiguration Technology demo☆39Updated 2 years ago
- Project Trellis database☆13Updated last year
- Industry standard I/O for Amaranth HDL☆28Updated 6 months ago
- Open source hardware down to the chip level!☆30Updated 3 years ago
- A template project for the ULX3S ECP5 FPGA board using only Open Source Software☆13Updated 6 years ago
- IP submodules, formatted for easier CI integration☆29Updated last year
- LiteX project for the ButterStick bootloader☆13Updated 2 years ago
- WebAssembly-based Yosys distribution for Amaranth HDL☆26Updated 2 weeks ago
- Language for composable analysis and generation of digital, analog, and RF signals☆55Updated 2 months ago
- 妖刀夢渡☆59Updated 6 years ago
- ☆63Updated 4 years ago
- Notes, scripts and apps to quickfeather board☆10Updated 3 years ago
- Betrusted main SoC design☆142Updated last year
- My pergola FPGA projects☆30Updated 3 years ago
- Documenting Lattice's 28nm FPGA parts☆142Updated last year
- a noodly Amaranth HDL-wrapper for FPGA SerDes' presenting a PIPE PHY interface☆32Updated 3 years ago
- Programmer for the Lattice ECP5 series, making use of FTDI based adaptors☆89Updated 6 months ago
- Verilog implementation of the 32-bit version of the Blake2 hash function☆21Updated last month
- Finding the bacteria in rotting FPGA designs.☆14Updated 4 years ago
- Bootloader for Fomu☆101Updated 2 years ago
- Yet Another Debug Transport☆21Updated 3 years ago
- Development board for Lattice Crosslink-NX 72QFN☆28Updated 4 years ago
- Hardware design files for Betrusted☆71Updated 3 years ago
- Low-cost ECP5 FPGA development board☆77Updated 4 years ago
- Example litex Risc-V SOC and some example code projects in multiple languages.☆67Updated last year
- Altera MAX V bitstream documentation -- CLEANUP PENDING☆19Updated 4 years ago