Alternatives and similar repositories for ChatEDAv1:

Users that are interested in ChatEDAv1 are comparing it to the libraries listed below

• JBlocklove / LLMs-for-EDA-Tutorial
  ☆51Updated 5 months ago
• MIRALab-USTC / ChiPBench
  ChiPBench:Benchmarking End-to-End Performance of AI-based Chip Placement Algorithms
  ☆28Updated last week
• lamda-bbo / Efficient-TDP
  Official implementation of DATE'25 paper "Timing-Driven Global Placement by Efficient Critical Path Extraction".
  ☆29Updated last month
• hkust-zhiyao / MasterRTL
  MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design
  ☆44Updated 6 months ago
• Yu-Maryland / Verilog-to-PyG
  ☆25Updated 11 months ago
• Yu-Maryland / Gamora
  Gamora: Graph Learning based Symbolic Reasoning for Large-Scale Boolean Networks (DAC'23)
  ☆49Updated 2 months ago
• DfX-NYUAD / GNN4IC
  Must-read papers on Graph Neural Networks (GNNs) for Integrated Circuits (ICs) design, security and reliability.
  ☆45Updated 3 weeks ago
• zshi0616 / python-deepgate
  ☆22Updated 9 months ago
• TILOS-AI-Institute / MLCAD-2023-FPGA-Macro-Placement-Contest
  ☆29Updated last year
• NVlabs / CircuitOps
  ☆76Updated 2 months ago
• krzhu / abcRL
  MLCAD 2020: Reinforcement for logic optimization sequence exploration
  ☆28Updated 4 years ago
• laiyao1 / ArithmeticTree
  The release for paper "Scalable and Effective Arithmetic Tree Generation for Adder and Multiplier Designs"
  ☆10Updated 6 months ago
• zshi0616 / DeepGate2
  ☆28Updated last year
• yaoxufeng / RTLRewriter-Bench
  ☆28Updated 10 months ago
• BUPT-GAMMA / PolarGate
  ☆10Updated 5 months ago
• lydiawunan / LOSTIN
  LOSTIN: Logic Optimization via Spatio-Temporal Information with Hybrid Graph Models
  ☆22Updated 2 years ago
• lydiawunan / HLS-Perf-Prediction-with-GNNs
  High-Level Synthesis Performance Prediction using GNNs: Benchmarking, Modeling, and Advancing
  ☆47Updated 9 months ago
• hkust-zhiyao / RTLLM
  An open-source benchmark for generating design RTL with natural language
  ☆97Updated 4 months ago
• HKUSTGZ-MICS-LYU / FlattenRTL
  This is a python repo for flattening Verilog
  ☆16Updated 2 months ago
• dekura / LLANA
  LLM-Enhanced Bayesian Optimization for Efficient Analog Constraint Generation
  ☆19Updated 5 months ago
• NYU-MLDA / OpenABC
  OpenABC-D is a large-scale labeled dataset generated by synthesizing open source hardware IPs. This dataset can be used for various graph…
  ☆124Updated 5 months ago
• scale-lab / BACS
  Benchmarks for Approximate Circuit Synthesis
  ☆15Updated 4 years ago
• aichipdesign / chipgptft
  Data is all you need: Finetuning LLMs for Chip Design via an Automated design-data augmentation framework (DAC 2024)
  ☆37Updated 3 months ago
• ispras / hdl-benchmarks
  Collection of digital hardware modules & projects (benchmarks)
  ☆52Updated 4 months ago
• HKUST-GZ-VLSI / Design-Dataset
  This is a repo to store circuit design datasets
  ☆16Updated last year
• krzhu / abc_py
  Simple Python interface for ABC
  ☆23Updated last year
• pku-dasys / easymac
  ☆16Updated 3 years ago
• cornell-zhang / HOGA
  Hop-Wise Graph Attention for Scalable and Generalizable Learning on Circuits
  ☆26Updated 7 months ago
• CODA-Team / AnalogGym
  ☆37Updated last month
• Entropy-xcy / sns
  ☆15Updated 2 years ago