ZipCPU / xulalx25soc
A System on a Chip Implementation for the XuLA2-LX25 board
☆16Updated 6 years ago
Alternatives and similar repositories for xulalx25soc:
Users that are interested in xulalx25soc are comparing it to the libraries listed below
- Wishbone interconnect utilities☆38Updated 7 months ago
- A collection of debugging busses developed and presented at zipcpu.com☆37Updated last year
- Using VexRiscv without installing Scala☆37Updated 3 years ago
- Wishbone controlled I2C controllers☆45Updated 2 months ago
- FPGA USB 1.1 Low-Speed Implementation☆33Updated 6 years ago
- Minimal DVI / HDMI Framebuffer☆78Updated 4 years ago
- CMod-S6 SoC☆37Updated 7 years ago
- Portable HyperRAM controller☆51Updated last month
- SoftCPU/SoC engine-V☆54Updated last year
- Demo SoC for SiliconCompiler.☆56Updated this week
- FPGA IP cores for the Antikernel OS, intended to be included as a submodule in SoC integrations☆62Updated 2 weeks ago
- Reusable Verilog 2005 components for FPGA designs☆39Updated last year
- Universal Advanced JTAG Debug Interface☆17Updated 8 months ago
- A set of Wishbone Controlled SPI Flash Controllers☆76Updated 2 years ago
- Yet Another RISC-V Implementation☆86Updated 3 months ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆31Updated 6 months ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- Tools for FPGA development.☆44Updated last year
- An open source FPGA PCI core & 8250-Compatible PCI UART core☆40Updated 4 years ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- A collection of SPI related cores☆15Updated 2 months ago
- A wishbone controlled scope for FPGA's☆74Updated last year
- Verilog wishbone components☆113Updated last year
- SDRAM controller with multiple wishbone slave ports☆28Updated 6 years ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆15Updated 8 years ago
- A quick reference/ cheatsheet for the ARM AMBA Advanced eXtensible Interface (AXI)☆26Updated 6 years ago
- USB 2.0 FS Device controller IP core written in SystemVerilog☆33Updated 6 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆117Updated 4 years ago