ZipCPU / xulalx25soc
A System on a Chip Implementation for the XuLA2-LX25 board
☆17Updated 6 years ago
Alternatives and similar repositories for xulalx25soc:
Users that are interested in xulalx25soc are comparing it to the libraries listed below
- A collection of debugging busses developed and presented at zipcpu.com☆40Updated last year
- Wishbone interconnect utilities☆39Updated last month
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆68Updated 2 years ago
- Universal Advanced JTAG Debug Interface☆17Updated 10 months ago
- RISC-V compliant Timer IP☆13Updated 10 months ago
- Multi-Technology RAM with AHB3Lite interface☆22Updated 10 months ago
- Using VexRiscv without installing Scala☆38Updated 3 years ago
- Implementation of RISC-V RV32IM. Simple in-order 3-stage pipeline. Low resources (e.g., FPGA softcore).☆33Updated 8 years ago
- CMod-S6 SoC☆40Updated 7 years ago
- Wishbone controlled I2C controllers☆47Updated 4 months ago
- A bare bones, basic, ZipCPU system designed for both testing and quick integration into new systems☆43Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆79Updated 2 years ago
- Yet Another RISC-V Implementation☆91Updated 6 months ago
- SoftCPU/SoC engine-V☆54Updated 2 weeks ago
- Featherweight RISC-V implementation☆52Updated 3 years ago
- FPGA USB 1.1 Low-Speed Implementation☆34Updated 6 years ago
- Is a collection of NULL Convention Logic (NCL) circuits and libraries written in Verilog to provide the experience of logically determine…☆15Updated 8 years ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆117Updated 4 years ago
- This is mainly a simulation library of xilinx primitives that are verilator compatible.☆33Updated 8 months ago
- Platform Level Interrupt Controller☆38Updated 10 months ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆80Updated 5 years ago
- Portable Verilog RTL interface to S27KL0641DABHI020 64Mbit HyperRAM IC☆86Updated 6 years ago
- A wishbone controlled scope for FPGA's☆78Updated last year
- DDR3 Controller v1.65, 16 read/write ports, configurable widths, priority, auto-burst size & cache on each port. VGA/HDMI multiwindow vi…☆76Updated 11 months ago
- Generic FPGA SDRAM controller, originally made for AS4C4M16SA☆79Updated 4 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆62Updated 7 years ago
- ☆63Updated 6 years ago
- Another tiny RISC-V implementation☆54Updated 3 years ago
- Reusable Verilog 2005 components for FPGA designs☆40Updated last month
- Minimal DVI / HDMI Framebuffer☆79Updated 4 years ago