Implementation of Wireless communication blocks such as FFT, OFDM receiver, Polar code decoder in a FPGA using Vivado HLS
☆31Dec 17, 2020Updated 5 years ago
Alternatives and similar repositories for FPGA-Wireless-communication-blocks
Users that are interested in FPGA-Wireless-communication-blocks are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- Polar codes are error correction codes developed by Erdal Arikan which achieves channel capacity and its reduced complexity makes it more…☆20Jul 22, 2021Updated 5 years ago
- CRC-Aided Polar Codes for 5G New Radio☆17Feb 4, 2024Updated 2 years ago
- Using the Quartus II software, a OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the d…☆15Dec 29, 2016Updated 9 years ago
- Implementation of the Xilinx FFT IP using a UART packetised data stream☆13Jul 24, 2022Updated 4 years ago
- This directory contains all the codes required to reproduce the results in our SPAWC 2017 paper titled "A compressive channel estimation …☆11Jun 22, 2018Updated 8 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- PolarDecoders implemented in Verilog. SC, SCL, CA-SCL and CA-PC-SCL are supported.☆10Sep 24, 2021Updated 5 years ago
- Verilog实现OFDM基带☆45Jan 22, 2016Updated 10 years ago
- This is the Matlab realization of Polar Decoders, including CA-SCL, Fast CA-SCL and BP decoder.☆195Nov 8, 2019Updated 6 years ago
- Learning of a communication system over a binary feedback channel☆13Apr 27, 2019Updated 7 years ago
- In this repo, an OFDM communication system is realized using Matlab. The system represents a simplified version of the WiFi (802.11) PHY…☆28Dec 17, 2020Updated 5 years ago
- This project demonstrates how Low Density Parity Check (LDPC) Code and Multiple Input Multiple Output (MIMO) can be employed in Vehicular…☆16Jan 24, 2022Updated 4 years ago
- Matlab and Python implementation of Different Information Theoretical Bounds: Shannon limit, Sphere Packaging Bound, Polyanskiy bound, …☆15Apr 28, 2023Updated 3 years ago
- Test SRIO connection between FPGA (Kintex-7) and DSP (C6678)☆20Nov 10, 2017Updated 8 years ago
- Learning Environment-aware and hardware-compatible beam-forming codebooks☆15Mar 8, 2020Updated 6 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Polar Decoder☆12Jan 19, 2023Updated 3 years ago
- ☆15Jan 22, 2024Updated 2 years ago
- 基于FPGA的FFT算法并行优化☆13Mar 7, 2024Updated 2 years ago
- A FPGA layer 2 network switch with the unique ability of having virtual ports that can transmit and receive UDP data.☆13Jul 24, 2026Updated 2 months ago
- Figure 4 in paper ``Cognitive Backscatter Network: A Spectrum Sharing Paradigm for Passive IoT''☆17Dec 29, 2019Updated 6 years ago
- An efficient implementation of the Viterbi decoding algorithm in Verilog☆63Mar 15, 2024Updated 2 years ago
- a MIPS-based embedded system on FPGA☆10Mar 10, 2017Updated 9 years ago
- Using the Quartus II software, an OFDM transmitter system was designed and implemented on Intel DE2i-150 board. Here QPSK is used as the …☆19Dec 29, 2016Updated 9 years ago
- Channel estimation of NOMA-OFDM system using Deep Learning.☆20Jan 31, 2023Updated 3 years ago
- GPU virtual machines on DigitalOcean Gradient AI • AdGet to production fast with high-performance AMD and NVIDIA GPUs you can spin up in seconds. The definition of operational simplicity.
- Transfer data from DDR memory to AXI4-Stream Data FIFO and back through AXI DMA☆23May 20, 2019Updated 7 years ago
- Machine Learning and Optimization for Communications Systems☆14Jun 8, 2026Updated 4 months ago
- Verilog Forward Error Correction Archive: BOX-Muller for fast AWGN generation, Universal Demapper from BPSK to QAM-512, different Forward…☆84Apr 28, 2023Updated 3 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 5 years ago
- ☆18Jun 26, 2023Updated 3 years ago
- This is a project integrating HLS IP and CortexA9 on Zynq. This CPU-FPGA project, for a Matrix Multiplication Dataflow, is implemented wi…☆21Sep 3, 2019Updated 7 years ago
- Implementation of the paper "Model Free Training of End-to-End Communication Systems"☆16Aug 6, 2022Updated 4 years ago
- Toy OFDM Communication System with FPGA☆12Dec 13, 2021Updated 4 years ago
- LDPC编码解码matlab代码和Verilog代码及资料☆50Aug 27, 2018Updated 8 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- An implementation of ABS Polar Code, including construction, encoding and decoding.☆12Jul 21, 2023Updated 3 years ago
- CNN-Aided Bit-Flipping for Belief Propagation Polar Decoder☆11Mar 12, 2021Updated 5 years ago
- MATLAB code for the coarray tensor completion-based 2-D DOA estimation algorithm☆24Jul 3, 2024Updated 2 years ago
- This repository contains verilog files to implement Reed Solomon encoding and decoding on FPGA. Each symbol is of 8 bits. Message length …☆27Dec 17, 2019Updated 6 years ago
- 5g polar code☆54Jun 21, 2019Updated 7 years ago
- Full piplined LDPC decoder (IEEE 802.16e) implement in FPGA using Xilinx HLS(C synthesis to Verilog Codes)..☆45May 2, 2019Updated 7 years ago
- Matlab code associated with the publication "Load Modulation for Backscatter Communication: Channel Capacity and Capacity-Approaching Fin…☆14Nov 15, 2022Updated 3 years ago