merledu / OpenTCAMLinks
An open-source Ternary Content Addressable Memory (TCAM) compiler.
☆29Updated 11 months ago
Alternatives and similar repositories for OpenTCAM
Users that are interested in OpenTCAM are comparing it to the libraries listed below
Sorting:
- BlackParrot on Zynq☆43Updated 4 months ago
- ☆76Updated 10 years ago
- TCAM (Ternary Content-Addressable Memory) in Verilog☆53Updated last year
- Open source RTL simulation acceleration on commodity hardware☆28Updated 2 years ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆37Updated 2 years ago
- ☆61Updated 4 years ago
- SystemVerilog Functional Coverage for RISC-V ISA☆29Updated last month
- RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores☆86Updated 2 weeks ago
- Open source process design kit for 28nm open process☆59Updated last year
- Verilog Content Addressable Memory Module☆107Updated 3 years ago
- Proposed RISC-V Composable Custom Extensions Specification☆71Updated 2 weeks ago
- Code to read various RTL simulator wave formats (fsdb, shm, vcd, wlf) into python and apply it as stimuli via cocotb/plain vpi.☆62Updated 3 years ago
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆42Updated 4 years ago
- ☆44Updated 5 years ago
- ☆32Updated 7 months ago
- Project repo for the POSH on-chip network generator☆48Updated 3 months ago
- Wavious DDR (WDDR) Physical interface (PHY) Hardware☆105Updated 3 years ago
- APB UVC ported to Verilator☆11Updated last year
- ☆66Updated 2 years ago
- A SytemVerilog implementation of Cyclic Redundancy Check runs at up to Terabits per second☆16Updated last year
- Hardware implementation of an OmniXtend Memory Endpoint/Lowest Point of Coherence.☆18Updated 2 months ago
- This is a tutorial on standard digital design flow☆78Updated 4 years ago
- OPAE porting to Xilinx FPGA devices.☆39Updated 4 years ago
- AutoSVA is a tool to automatically generate formal testbenches for unit-level RTL verification. The goal is to, based on annotations made…☆85Updated last year
- ☆96Updated last year
- Pure digital components of a UCIe controller☆64Updated this week
- Platform Level Interrupt Controller☆41Updated last year
- IEEE 754 single and double precision floating point library in systemverilog and vhdl☆67Updated 6 months ago
- A configurable SRAM generator☆53Updated last week
- Verilog Ethernet Switch (layer 2)☆45Updated last year