An open-source Ternary Content Addressable Memory (TCAM) compiler.
☆37Jul 19, 2024Updated 2 years ago
Alternatives and similar repositories for OpenTCAM
Users that are interested in OpenTCAM are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- TCAM (Ternary Content-Addressable Memory) in Verilog☆59Oct 9, 2023Updated 2 years ago
- ☆16Dec 16, 2021Updated 4 years ago
- A caravan equipped with API for creating bus protocols in Chisel with ease.☆14Jan 15, 2026Updated 8 months ago
- Network packet parser generator☆53Sep 11, 2020Updated 6 years ago
- Project ideas list for Google Summer of Code.☆18Jan 28, 2026Updated 7 months ago
- Virtual machines for every use case on DigitalOcean • AdGet dependable uptime with 99.99% SLA, simple security tools, and predictable monthly pricing with DigitalOcean's virtual machines, called Droplets.
- ☆17Sep 19, 2022Updated 4 years ago
- Modular SRAM-based indirectly-indexed 2D hierarchical-search Ternary Content Addressable Memory (II-2D-TCAM)☆23Nov 10, 2024Updated last year
- Business Rule Engine Hardware Accelerator☆15Jun 18, 2020Updated 6 years ago
- Accelerating the regular expression matching on FPGA for applications in Networking and Bioinformatics.☆13Nov 24, 2017Updated 8 years ago
- A cycle-accurate RISC-V CPU simulator + RTL modeling library in pure Python.☆20Aug 14, 2026Updated last month
- An accelerator to which you can offload RE matching☆14Dec 22, 2024Updated last year
- Alliance VLSI CAD Tools (LIP6)☆24Aug 28, 2026Updated 3 weeks ago
- fakeram generator for use by researchers who do not have access to commercial ram generators☆45Jan 13, 2023Updated 3 years ago
- Conda recipes for FPGA EDA tools for simulation, synthesis, place and route and bitstream generation.☆102Jan 30, 2025Updated last year
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- Converts GDSII files to STL files.☆44Dec 12, 2023Updated 2 years ago
- ☆13Jul 5, 2026Updated 2 months ago
- LPC (Low Pin Count) interface peripheral module in pure Verilog☆17Jan 15, 2024Updated 2 years ago
- Azadi (Freedom) is a 32-bit RISC-V CPU based System on Chip.☆34Aug 28, 2023Updated 3 years ago
- ☆15Dec 2, 2021Updated 4 years ago
- Microbenchmarking experiments on Zen 2 machines☆22Jun 25, 2022Updated 4 years ago
- Groundhog - Serial ATA Host Bus Adapter☆24Jun 10, 2018Updated 8 years ago
- uvm_apb is a uvm package for modeling and verifying APB (Advanced Periperal Bus) protocol☆21Feb 7, 2025Updated last year
- Planter is a modular framework for realising in one-click in-network machine learning algorithms.☆59Feb 10, 2026Updated 7 months ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Framework for FPGA-accelerated Middlebox Development☆50Feb 18, 2023Updated 3 years ago
- Notebooks for Hardware-Aware Training of Spiking Neural Networks. Open-Source Neuromorphic Circuit Design Tutorial at ESSCIRC 2023.☆26Sep 11, 2023Updated 3 years ago
- A lightweight core for the CV32E40 implementing the RISC-V vector extension specification. (v0.8)☆35Jan 19, 2021Updated 5 years ago
- ☆22Dec 27, 2024Updated last year
- Resources and guide for preparing for Stanford's electrical engineering qualification exams.☆25Feb 4, 2020Updated 6 years ago
- ☆42Jun 9, 2022Updated 4 years ago
- RTLMeter benchmark suite☆33Updated this week
- Source code of the paper "Low-Cost and Programmable CRC Implementation based on FPGA"☆43Jan 8, 2021Updated 5 years ago
- TIDENet is an ASIC written in Verilog for Tiny Image Detection at Edge with neural networks (TIDENet) using DNNWeaver 2.0, the Google Sky…☆18Jan 30, 2023Updated 3 years ago
- Deploy open-source AI quickly and easily - Special Bonus Offer • AdRunpod Hub is built for open source. One-click deployment and autoscaling endpoints without provisioning your own infrastructure.
- This project produces a clean GDSII Layout with all its details that are used to print photomasks used in the fabrication of a behavioral…☆18Oct 16, 2021Updated 4 years ago
- Verilog Content Addressable Memory Module☆118Mar 2, 2022Updated 4 years ago
- ☆16May 11, 2022Updated 4 years ago
- ☆39Jul 11, 2022Updated 4 years ago
- 上位机软件与下位机FPGA采集卡实现UDP通信,接收发送的正弦波信号帧,并保存到本地文件☆14Apr 27, 2022Updated 4 years ago
- A Convolutional Neural Network (CNN) hardware accelerator for image recognition☆16Jul 14, 2019Updated 7 years ago
- ☆56Jun 22, 2022Updated 4 years ago