Domipheus / TPULinks
TPU, The Test Processing Unit. Or Terrible Processing Unit. A simple 16-bit CPU in VHDL for education as to the dataflow within a CPU. Designed to run on miniSpartan6+.
☆148Updated 8 years ago
Alternatives and similar repositories for TPU
Users that are interested in TPU are comparing it to the libraries listed below
Sorting:
- Basic RISC-V CPU implementation in VHDL.☆167Updated 4 years ago
- Oldland CPU - a 32-bit RISC FPGA CPU including RTL + tools☆125Updated 9 years ago
- A simple RISC-V processor for use in FPGA designs.☆277Updated 10 months ago
- A damn small msp430-compatible customizable soft-core microcontroller-like processor system written in platform-independent VHDL.☆203Updated 3 years ago
- A utility for Composing FPGA designs from Peripherals☆181Updated 6 months ago
- An Open Source configuration of the Arty platform☆130Updated last year
- 32-bit RISC-V system on chip for iCE40 FPGAs☆309Updated 2 years ago
- A FPGA core for a simple SDRAM controller.☆119Updated 3 years ago
- A 32-bit MIPS / RISC-V core & SoC, 1.55 DMIPS/MHz, 2.96 CM/Mhz☆413Updated 2 weeks ago
- A rudimental RISCV CPU supporting RV32I instructions, in VHDL☆122Updated 4 years ago
- LatticeMico32 soft processor☆106Updated 10 years ago
- A Video display simulator☆171Updated last month
- Small Processing Unit 32: A compact RV32I CPU written in Verilog☆69Updated 3 years ago
- Yet Another RISC-V Implementation☆94Updated 9 months ago
- The Easy 8-bit Processor☆183Updated 11 years ago
- Riscy-SoC is SoC based on RISC-V CPU core, designed in Verilog☆81Updated 5 years ago
- Parallel Array of Simple Cores. Multicore processor.☆100Updated 6 years ago
- A 32-bit RISC-V soft processor☆311Updated 4 months ago
- Core description files for FuseSoC☆124Updated 5 years ago
- The openMSP430 is a synthesizable 16bit microcontroller core written in Verilog.☆65Updated 7 years ago
- A Simple FPGA Core for Creating VGA/DVI/HDMI/OpenLDI Signals☆239Updated 6 years ago
- RISC-V Rocket Core on Parallella & ZedBoard Zynq FPGA Boards☆101Updated 6 years ago
- Instruction set simulator for RISC-V, MIPS and ARM-v6m☆101Updated 3 years ago
- SoftCPU/SoC engine-V☆54Updated 3 months ago
- The original high performance and small footprint system-on-chip based on Migen™☆330Updated 2 months ago
- GPL v3 2D/3D graphics engine in verilog☆669Updated 10 years ago
- Western Digital’s Open Source RISC-V SweRV Instruction Set Simulator☆203Updated 4 years ago
- WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.☆238Updated last month
- SoC based on VexRiscv and ICE40 UP5K☆158Updated 3 months ago
- Open source implementation of a x86 processor☆322Updated 7 years ago