levibyte / channel_router
demo on simple channel router
☆12Updated 5 years ago
Related projects ⓘ
Alternatives and complementary repositories for channel_router
- IO and Pin Placer for Floorplan-Placement Subflow☆23Updated 4 years ago
- This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk☆26Updated 3 years ago
- LibreSilicon's Standard Cell Library Generator☆17Updated 6 months ago
- Some simple examples for the Magic VLSI physical chip layout tool.☆27Updated 3 years ago
- EDA physical synthesis optimization kit☆50Updated last year
- An open source PDK using TIGFET 10nm devices.☆43Updated last year
- Collection of test cases for Yosys☆17Updated 2 years ago
- Open Source Detailed Placement engine☆34Updated 4 years ago
- Java library for parsing and manipulating graph representations of gate-level Verilog netlists☆13Updated 7 years ago
- A LEF/DEF Utility.☆27Updated 5 years ago
- EDA wiki☆50Updated last year
- Benchmarks for Yosys development☆22Updated 4 years ago
- Source codes and calibration scripts for clock tree synthesis☆39Updated 4 years ago
- SRAM☆8Updated 4 years ago
- Open Source Detailed Placement engine☆11Updated 4 years ago
- Global Router Built for ICCAD Contest 2019☆30Updated 4 years ago
- A library and command-line tool for querying a Verilog netlist.☆26Updated 2 years ago
- ☆39Updated 4 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆47Updated 9 years ago
- DATC Robust Design Flow.☆37Updated 4 years ago
- The PE for the second generation CGRA (garnet).☆16Updated 2 months ago
- OpenDesign Flow Database☆16Updated 6 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆39Updated last year
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆28Updated 4 months ago
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆31Updated 3 weeks ago
- BSG Replicant: Cosimulation and Emulation Infrastructure for HammerBlade☆26Updated this week
- Steiner Shallow-Light Tree for VLSI Routing☆46Updated 4 months ago
- BAG framework☆41Updated 3 months ago
- Intel's Analog Detailed Router☆37Updated 5 years ago
- A Fast C++ Header-only Parser for Standard Parasitic Exchange Format (SPEF).☆51Updated 2 years ago