levibyte / channel_routerLinks
demo on simple channel router
☆13Updated 6 years ago
Alternatives and similar repositories for channel_router
Users that are interested in channel_router are comparing it to the libraries listed below
Sorting:
- A LEF/DEF Utility.☆32Updated 6 years ago
- Source codes and calibration scripts for clock tree synthesis☆40Updated 5 years ago
- An open source PDK using TIGFET 10nm devices.☆51Updated 2 years ago
- DATC Robust Design Flow.☆36Updated 5 years ago
- Wavious DDR (WDDR) Physical interface (PHY) Software☆22Updated 3 years ago
- KLayout technology files for ASAP7 FinFET educational process☆21Updated 2 years ago
- Python library for working Standard Delay Format (SDF) Timing Annotation files.☆30Updated last year
- Open-sourced utilities for initial flow setup, calibration, and other user functions for OpenROAD project☆19Updated 6 years ago
- ☆44Updated 5 years ago
- Cross EDA Abstraction and Automation☆40Updated last week
- LEF/DEF-based port of Iowa State's open-source FastRoute 4.1☆58Updated 5 years ago
- EDA physical synthesis optimization kit☆62Updated last year
- ☆20Updated last year
- LibreSilicon's Standard Cell Library Generator☆20Updated 3 weeks ago
- IO and Pin Placer for Floorplan-Placement Subflow☆22Updated 5 years ago
- Workshop on Open-Source EDA Technology (WOSET)☆48Updated 11 months ago
- YosysHQ SVA AXI Properties☆43Updated 2 years ago
- ☆18Updated last year
- Python library of AST nodes for SystemVerilog/VHDL, code generator, transpiler and translator☆41Updated last week
- Supplemental technology files for ASAP7 PDK with Synopsys design flow☆18Updated 2 years ago
- Open Source Detailed Placement engine☆39Updated 5 years ago
- A tool that converts SystemVerilog to Verilog. Uses Design Compiler, so it is 100% compatible.☆43Updated 2 years ago
- A library and command-line tool for querying a Verilog netlist.☆28Updated 3 years ago
- A collection of big designs to run post-synthesis simulations with yosys☆49Updated 10 years ago
- UCSD Detailed Router☆91Updated 4 years ago
- Universal Verification Methodology (UVM) base libraries, with edits for Verilator☆26Updated 3 weeks ago
- Open Source PHY v2☆31Updated last year
- SMT-based Simultaneous Place-&-Route for Standard Cell Synthesis for PROBE 2.0☆18Updated 5 years ago
- Qrouter detail router for digital ASIC designs☆57Updated 6 months ago
- Extended and external tests for Verilator testing☆17Updated last month