Alternatives and similar repositories for channel_router

Users that are interested in channel_router are comparing it to the libraries listed below

• The-OpenROAD-Project-Attic / ioPlacer
  IO and Pin Placer for Floorplan-Placement Subflow
  ☆22Updated 4 years ago
• The-OpenROAD-Project / OpenDP
  Open Source Detailed Placement engine
  ☆11Updated 5 years ago
• The-OpenROAD-Project-Attic / FastRoute
  LEF/DEF-based port of Iowa State's open-source FastRoute 4.1
  ☆54Updated 4 years ago
• YosysHQ / yosys-tests
  Collection of test cases for Yosys
  ☆18Updated 3 years ago
• The-OpenROAD-Project / TritonCTS
  Source codes and calibration scripts for clock tree synthesis
  ☆40Updated 5 years ago
• jinwookjungs / lefdef_util
  A LEF/DEF Utility.
  ☆28Updated 5 years ago
• The-OpenROAD-Project / TritonMacroPlace
  Macro placement tool for OpenROAD flow
  ☆23Updated 4 years ago
• scale-lab / OpenPhySyn
  EDA physical synthesis optimization kit
  ☆54Updated last year
• jinwookjungs / datc_robust_design_flow
  DATC Robust Design Flow.
  ☆37Updated 5 years ago
• YosysHQ / yosys-bench
  Benchmarks for Yosys development
  ☆24Updated 5 years ago
• sanggido / OpenDP
  Open Source Detailed Placement engine
  ☆38Updated 5 years ago
• eda-ricercatore / Modica-SRAM
  Design of a 32-kbit synchronous SRAM with 32-bit words, using 180 nm process technology. Developed MATLAB scripts to evaluate architectu…
  ☆15Updated 4 years ago
• ieee-ceda-datc / RDF-2019
  DATC RDF
  ☆50Updated 4 years ago
• jinwookjungs / open_design_flow
  OpenDesign Flow Database
  ☆16Updated 6 years ago
• parallella / openeda
  Open source EDA chip design flow
  ☆50Updated 8 years ago
• xprova / netlist-graph
  Java library for parsing and manipulating graph representations of gate-level Verilog netlists
  ☆13Updated 8 years ago
• aolofsson / POSH
  ☆44Updated 5 years ago
• AUCOHL / OGRE
  Global Router Built for ICCAD Contest 2019
  ☆31Updated 5 years ago
• UNSAMDCI / PDK_ONC5
  Educational Design Kit for Synopsys Tools with a set of Characterized Standard Cell Library
  ☆33Updated 3 years ago
• Coloquinte / Coloquinte_placement
  An analytical VLSI placer
  ☆28Updated 3 years ago
• The-OpenROAD-Project / PcbRouter
  ☆30Updated 4 years ago
• bluecheetah / bag
  BAG framework
  ☆40Updated 9 months ago
• andrsmllr / magic_vlsi_examples
  Some simple examples for the Magic VLSI physical chip layout tool.
  ☆29Updated 4 years ago
• chengengjie / salt
  Steiner Shallow-Light Tree for VLSI Routing
  ☆51Updated 10 months ago
• FPGA-Research / eFPGA---RTL-to-GDS-with-SKY130
  This repo shows an implementation of an FPGA from RTL to GDS with open Skywater-130 pdk
  ☆30Updated 3 years ago
• mgraczyk / coursera-vlsicad
  Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout
  ☆11Updated 11 years ago
• asyncvlsi / AMC
  AMC: Asynchronous Memory Compiler
  ☆48Updated 4 years ago
• thesourcerer8 / StdCellLib
  LibreSilicon's Standard Cell Library Generator
  ☆18Updated last year
• YosysHQ / yosys-bigsim
  A collection of big designs to run post-synthesis simulations with yosys
  ☆49Updated 9 years ago
• The-OpenROAD-Project / OpenRCX
  ☆22Updated 4 years ago