30 Days of Verilog: Dive into digital circuits with a month of Verilog coding challenges. From logic gates to FSMs, sharpen your skills and simulate your designs. Let's code and conquer circuits!
☆61Sep 30, 2023Updated 2 years ago
Alternatives and similar repositories for 30-days-of-verilog
Users that are interested in 30-days-of-verilog are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆10Oct 16, 2023Updated 2 years ago
- System Verilog using Functional Verification☆12Apr 8, 2024Updated 2 years ago
- ☆18Feb 26, 2024Updated 2 years ago
- 32 bit RISC-V CPU implementation in Verilog☆34Feb 9, 2022Updated 4 years ago
- Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …☆149Jul 17, 2022Updated 3 years ago
- Wordpress hosting with auto-scaling - Free Trial Offer • AdFully Managed hosting for WordPress and WooCommerce businesses that need reliable, auto-scalable performance. Cloudways SafeUpdates now available.
- The Repository contains the code of various Digital Circuits☆12Aug 7, 2023Updated 2 years ago
- ☆12May 8, 2022Updated 4 years ago
- This repo contains code for specific quantum papers i've read. Check my Medium blogs for more.☆17Jun 27, 2024Updated last year
- Tutorial series on verilog with code examples. Contains basic verilog code implementations and concepts.☆62Nov 25, 2020Updated 5 years ago
- Verilog code that does 2D Low Pass Filter on a greyscale image☆10Sep 22, 2015Updated 10 years ago
- An adaptive filter was designed that can update its weights according to the application needed (lowpass, highpass or bandpass) using the…☆12Jan 3, 2019Updated 7 years ago
- Universal Asynchronous Receiver/Transmitter (UART) with FIFOs Soft IP☆15Feb 18, 2025Updated last year
- A port of the Cells extension to CLOS to Python.☆13Apr 20, 2016Updated 10 years ago
- Verilog Project☆20Aug 30, 2021Updated 4 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC …☆12Aug 6, 2025Updated 9 months ago
- ☆119Dec 24, 2023Updated 2 years ago
- In this project, low-pass filters and Kalman filters with different window function designs are used to denoise speech signals polluted i…☆11Feb 11, 2023Updated 3 years ago
- UVM Testbench for synchronus fifo☆19Aug 28, 2020Updated 5 years ago
- MAX31865 PT100 PT1000 RTD temperature sensor breakout board☆18Apr 29, 2026Updated last week
- ☆13Dec 1, 2024Updated last year
- MATLAB Guide☆24Apr 3, 2022Updated 4 years ago
- 16 bit CPU created in Vivado with Verilog☆22Jun 30, 2022Updated 3 years ago
- A simple, working, 32-bit ALU design.☆14Dec 26, 2014Updated 11 years ago
- Managed hosting for WordPress and PHP on Cloudways • AdManaged hosting for WordPress, Magento, Laravel, or PHP apps, on multiple cloud providers. Deploy in minutes on Cloudways by DigitalOcean.
- Design and UVM Verification of an ALU☆13Jun 14, 2024Updated last year
- ☆55Jun 19, 2021Updated 4 years ago
- Verification IP for APB protocol☆77Dec 18, 2020Updated 5 years ago
- A complete UVM TB for verification of single port 64KB RAM☆18Apr 16, 2021Updated 5 years ago
- Temperature sensor using 24-bit ADC_ ADS1220☆23Dec 18, 2021Updated 4 years ago
- Describes the best coding practices and guidelines☆11Jan 4, 2024Updated 2 years ago
- Academic project for the course of Digital Systems Design. The aim of the project was to design and implement an IIR audio filter on FPGA☆12Mar 29, 2018Updated 8 years ago
- VIP for AXI Protocol☆171May 24, 2022Updated 3 years ago
- Motion Estimation implementation by using Verilog HDL☆13Jun 17, 2024Updated last year
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Fast, compact floating point math for ARM Cortex-M0+ MCUs.☆12Apr 16, 2025Updated last year
- Contains the System Verilog description for a simplified USB host that implements the transaction, data-link, and physical layers of the …☆15Jan 13, 2015Updated 11 years ago
- # 3.Interview_Questions In my experience, the questions i faced in the interviews and the people surrounded me must have faced a couple o…☆25Jul 9, 2025Updated 10 months ago
- Hey guys this the project where i have implemented the Kalman filter for MPPT for solar PV module☆20Nov 8, 2017Updated 8 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆78Oct 7, 2022Updated 3 years ago
- Practice exercises for SystemVerilog, UVM ..☆27Jun 7, 2020Updated 5 years ago
- Generic AXI master stub☆19Jul 17, 2014Updated 11 years ago