Alternatives and similar repositories for verilog-starter-tutorials

Users that are interested in verilog-starter-tutorials are comparing it to the libraries listed below

• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆111Updated 4 years ago
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆140Updated 3 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆146Updated 6 years ago
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆112Updated last year
• merldsu / RISCV_Single_Cycle_Core
  This repository contains the design files of RISC-V Single Cycle Core
  ☆55Updated last year
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆73Updated last year
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆98Updated 3 months ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆133Updated 4 years ago
• mongrelgem / Verilog-Adders
  Implementing Different Adder Structures in Verilog
  ☆72Updated 6 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆117Updated 2 weeks ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆111Updated last month
• uobdv / Design-Verification
  Course content for the University of Bristol Design Verification course.
  ☆61Updated 2 weeks ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆136Updated 5 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆145Updated 9 years ago
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆113Updated last week
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆272Updated 4 months ago
• nishthaparashar / Floating-Point-ALU-in-Verilog
  32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.
  ☆91Updated 6 years ago
• michaelehab / AES-Verilog
  Advanced encryption standard (AES128, AES192, AES256) Encryption and Decryption Implementation in Verilog HDL
  ☆119Updated 3 years ago
• snbk001 / 100DaysofRTL
  100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…
  ☆35Updated 2 years ago
• kunalg123 / vsdflow
  VSDFLOW is an automated solution to programmers, hobbyists and small scale semiconductor technology entrepreneurs who can craft the…
  ☆162Updated 2 years ago
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆128Updated 4 years ago
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆49Updated 3 years ago
• snbk001 / Verilog-Design-Examples
  Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…
  ☆158Updated last year
• AkeelMedina22 / RISC-V-Pipelined-Processor
  A Verilog based 5-stage fully functional pipelined RISC-V Processor code.
  ☆50Updated 4 years ago
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 6 months ago
• ekb0412 / 100DaysofRTL
  "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado
  ☆96Updated 2 years ago
• maze1377 / pipeline-mips-verilog
  A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall
  ☆53Updated 8 months ago
• agalimberti / NoCRouter
  RTL Network-on-Chip Router Design in SystemVerilog by Andrea Galimberti, Filippo Testa and Alberto Zeni
  ☆129Updated 7 years ago
• NAvi349 / riscv-proc
  32-bit 5-Stage Pipelined RISC V RV32I Core
  ☆53Updated last year
• The-OpenROAD-Project / yosys
  Logic synthesis and ABC based optimization
  ☆50Updated last week