Alternatives and similar repositories for Digital-Resources

Users that are interested in Digital-Resources are comparing it to the libraries listed below

• stevehoover / RISC-V_MYTH_Workshop
  Accompanying live info and links for VLSI Design Systems and Redwood EDA "Microprocessor for You in Thirty Hours" Workshop
  ☆93Updated 5 months ago
• shivanishah269 / risc-v-core
  This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…
  ☆79Updated last year
• TL-X-org / TL-V_Projects
  An overview of TL-Verilog resources and projects
  ☆81Updated 4 months ago
• arm-university / Introduction-to-SoC-Design-Education-Kit
  Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…
  ☆139Updated 3 months ago
• mikeroyal / Verilog-SystemVerilog-Guide
  Verilog/SystemVerilog Guide
  ☆72Updated last year
• arm-university / VLSI-Fundamentals-Education-Kit
  Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …
  ☆264Updated 3 months ago
• mattvenn / awesome-opensource-asic-resources
  ☆339Updated 2 years ago
• hdl / awesome
  A curated list of awesome resources for HDL design and verification
  ☆157Updated last week
• AngeloJacobo / RISC-V
  Design implementation of the RV32I Core in Verilog HDL with Zicsr extension
  ☆104Updated last year
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆108Updated last week
• tscheipel / HaDes-V
  HaDes-V is an Open Educational Resource for learning microcontroller design. It guides you through creating a pipelined 32-bit RISC-V pro…
  ☆80Updated 2 months ago
• AngeloJacobo / FPGA_Book_Experiments
  My completed projects from "FPGA Prototyping by Verilog Examples" book by Pong P. Chu
  ☆143Updated 4 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆140Updated 6 years ago
• nickson-jose / vsdstdcelldesign
  This repository contains all the information needed to run RTL2GDSII flow using openlane flow. Apart from that, it also contain procedure…
  ☆74Updated 4 years ago
• brabect1 / sta_basics_course
  Introductory course into static timing analysis (STA).
  ☆97Updated last month
• The-OpenROAD-Project / OPENROAD_USERS_READ_ME_FIRST
  OpenROAD users should look at this repository first for instructions on getting started
  ☆101Updated 4 years ago
• AngeloJacobo / OpenLANE-Sky130-Physical-Design-Workshop
  Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130
  ☆65Updated 2 years ago
• asinghani / open-eda-course
  Curriculum for a university course to teach chip design using open source EDA tools
  ☆107Updated last year
• AUCOHL / DFFRAM
  Standard Cell Library based Memory Compiler using FF/Latch cells
  ☆155Updated last month
• arm-university / Advanced-System-on-Chip-Design-Education-Kit
  Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description an…
  ☆113Updated 3 months ago
• wyvernSemi / riscV
  Open source ISS and logic RISC-V 32 bit project
  ☆57Updated 2 months ago
• georgeyhere / Toast-RV32i
  Pipelined RISC-V RV32I Core in Verilog
  ☆39Updated 2 years ago
• akilm / Physical-Design
  Physical Design Flow from RTL to GDS using Opensource tools.
  ☆105Updated 4 years ago
• Akash-Perla / ASIC-Design
  This repository contains the tasks performed for VL508- Physical Design of ASIC Course (Fall 2024)
  ☆13Updated 9 months ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆112Updated last week
• manili / VSDBabySoC
  VSDBabySoC is a small mixed-signal SoC including PLL, DAC, and a RISCV-based processor named RVMYTH.
  ☆44Updated 3 years ago
• hamsternz / Rudi-RV32I
  A rudimental RISCV CPU supporting RV32I instructions, in VHDL
  ☆122Updated 4 years ago
• ARC-Lab-UF / sv-tutorial
  SystemVerilog Tutorial
  ☆164Updated 3 months ago
• fukatani / awesome-hdl
  A curated list of awesome HDL, libraries, typical implementation and references.
  ☆38Updated 8 years ago
• ash-olakangal / RISC-V-Processor
  Verilog implementation of multi-stage 32-bit RISC-V processor
  ☆119Updated 4 years ago