arm-university / Advanced-System-on-Chip-Design-Education-Kit
Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description and software programming languages
☆96Updated 8 months ago
Alternatives and similar repositories for Advanced-System-on-Chip-Design-Education-Kit:
Users that are interested in Advanced-System-on-Chip-Design-Education-Kit are comparing it to the libraries listed below
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆122Updated 8 months ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆235Updated 8 months ago
- SystemVerilog Tutorial☆138Updated last week
- This repo provide an index of VLSI content creators and their materials☆147Updated 7 months ago
- Basic RISC-V Test SoC☆119Updated 5 years ago
- A reference book on System-on-Chip Design☆25Updated 11 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆84Updated last year
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆68Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆118Updated last year
- Developed with the aim of providing engineers and designers with a centralized resource, this repository serves as a valuable reference f…☆57Updated 11 months ago
- ☆152Updated 2 years ago
- Synthesizable RTL-Based video stream Convolutional Neural Network ( non HLS )☆58Updated 4 months ago
- ☆79Updated 6 months ago
- 100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Coun…☆34Updated 2 years ago
- UVM and System Verilog Manuals☆40Updated 6 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆62Updated 2 weeks ago
- ☆106Updated last year
- This is the repository for the IEEE version of the book☆57Updated 4 years ago
- ☆12Updated last month
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB…☆58Updated 2 years ago
- RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications☆164Updated 4 months ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated last year
- Implementing Different Adder Structures in Verilog☆64Updated 5 years ago
- ☆16Updated 8 months ago
- AXI4 Full, Lite, and AxiStream verification components. AXI4 Interface Master, Responder, and Memory verification components. AxiStream t…☆134Updated 2 weeks ago
- 32-Bit Algorithms of Floating Point Operations are implemented on Verilog with logic Operations.☆83Updated 5 years ago
- Verilog/SystemVerilog Guide☆61Updated last year
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆56Updated 2 years ago