arm-university / Advanced-System-on-Chip-Design-Education-Kit
Design, implement, and test an Arm Cortex-A-based SoCs on FPGA hardware using functional specifications, standard hardware description and software programming languages
☆98Updated 8 months ago
Alternatives and similar repositories for Advanced-System-on-Chip-Design-Education-Kit:
Users that are interested in Advanced-System-on-Chip-Design-Education-Kit are comparing it to the libraries listed below
- Gain an introductory knowledge to the basics of SoC design and key skills required to implement a simple SoC on an FPGA, and write embedd…☆125Updated 8 months ago
- SystemVerilog Tutorial☆138Updated 3 weeks ago
- Gain an understanding of the fundamentals of Very Large-Scale Integration (VLSI), including how the theories and concepts can be applied …☆237Updated 8 months ago
- Design implementation of the RV32I Core in Verilog HDL with Zicsr extension☆85Updated last year
- Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy mach…☆120Updated last year
- This repository contains the design files of RISC-V Single Cycle Core☆40Updated last year
- Basic RISC-V Test SoC☆121Updated 6 years ago
- This repo provide an index of VLSI content creators and their materials☆149Updated 8 months ago
- ☆154Updated 2 years ago
- "100 days of RTL" is a personal project to learn Verilog HDL RTL design in 100 days, using Xilinx Vivado☆75Updated last year
- A reference book on System-on-Chip Design☆25Updated last year
- ☆12Updated 3 weeks ago
- Documentation for the 5 day workshop: Advanced Physical Design using OpenLane/Sky130☆56Updated 2 years ago
- Introductory course into static timing analysis (STA).☆90Updated 5 months ago
- I am a VLSI enthusiast and I'm going to start my journey of 100 days of RTL.☆23Updated last year
- Implementation of RISC-V RV32I☆17Updated 2 years ago
- ☆81Updated 7 months ago
- In this tutorial, you learn how to implement a design from RTL-to-GDSII using Cadence® tools.☆57Updated last year
- The objective of this project was to design and implement a 5 stage pipeline CPU to support the RISC-V instruction architecture. This pip…☆24Updated 3 years ago
- This project was done as a part of RISC-V based MYTH (Microprocessor for you in Thirty Hours) workshop organized by Kunal Ghosh and Steve…☆75Updated last year
- Verilog/SystemVerilog Guide☆64Updated last year
- AXI4 and AXI4-Lite interface definitions☆92Updated 4 years ago
- The project is about building an 8-row by 8-bit 6T SRAM memory array, & a 3-to-8 decoder that's used to access the SRAM array. The layout…☆71Updated 2 years ago
- Various RTL design blocks along with verification testbenches with SVAs. Designed using SystemVerilog☆25Updated 2 years ago
- Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.☆68Updated this week
- Architectural design of data router in verilog☆29Updated 5 years ago
- "Mastering Verilog Programming for Digital Circuit Design: RTL and TestBench Codes Practice with HDL-BITS"☆15Updated last year
- This is the repository for the IEEE version of the book☆58Updated 4 years ago
- Implementing Different Adder Structures in Verilog☆65Updated 5 years ago
- An overview of TL-Verilog resources and projects☆78Updated 3 weeks ago