Alternatives and similar repositories for MIPS:

Users that are interested in MIPS are comparing it to the libraries listed below

• RickyTino / MangoMIPS32
  A softcore microprocessor of MIPS32 architecture.
  ☆39Updated 6 months ago
• sxtyzhangzk / mips-cpu
  A MIPS CPU implemented in Verilog
  ☆65Updated 7 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆114Updated 9 years ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆169Updated 6 years ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆113Updated 4 years ago
• name1e5s / Sirius
  Asymmetric dual issue in-order microprocessor.
  ☆34Updated 5 years ago
• nscscc2019ucas / nscscc2019ucas
  ☆33Updated 5 years ago
• Michaelvll / RISCV_CPU
  A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
  ☆78Updated 5 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆128Updated 2 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆106Updated 3 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆69Updated 4 years ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆108Updated last year
• Superscalar-HIT-Core / Superscalar-HIT-Core-NSCSCC2020
  a Quad-issue, Out-of-order Superscalar MIPS Processor Implemented in SystemVerilog
  ☆45Updated last year
• xyongcn / LoongsonCsprj2017
  Computer System Project for Loongson FPGA Board in 2017
  ☆52Updated 6 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆145Updated last year
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆250Updated 7 years ago
• watz0n / learn-rv32i-asap
  A Simple As Possible RISCV-32I core with debug module.
  ☆43Updated 5 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆128Updated this week
• RALC88 / riscv-vectorized-benchmark-suite
  RiVEC Bencmark Suite
  ☆108Updated last month
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆122Updated 5 years ago
• rajshadow / 4-way-set-associative-cache-verilog
  Verilog implementation of a 4-way Set associative cache with a write buffer (write) policy and FIFO replacement policy
  ☆40Updated 8 years ago
• OSCPU / chisel-playground
  ☆57Updated last month
• librecores / riscv-sodor
  educational microarchitectures for risc-v isa
  ☆65Updated 5 years ago
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆36Updated 6 years ago
• OpenXiangShan / GEM5
  ☆72Updated this week
• sifive / block-inclusivecache-sifive
  ☆77Updated 2 years ago
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆63Updated 5 years ago
• openhwgroup / cva6-sdk
  CVA6 SDK containing RISC-V tools and Buildroot
  ☆61Updated 6 months ago