Alternatives and similar repositories for MIPS

Users that are interested in MIPS are comparing it to the libraries listed below

• sxtyzhangzk / mips-cpu
  A MIPS CPU implemented in Verilog
  ☆70Updated 8 years ago
• cnrv / rocket-chip-read
  Comment on the rocket-chip source code
  ☆179Updated 7 years ago
• airin711 / Verilog-caches
  Various caches written in Verilog-HDL
  ☆127Updated 10 years ago
• Michaelvll / RISCV_CPU
  A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL
  ☆95Updated 6 years ago
• Evensgn / RISC-V-CPU
  RISC-V CPU with 5-stage pipeline, implemented in Verilog HDL.
  ☆326Updated 7 years ago
• meton-robean / ResearchNote
  通过issue和README来记录日常学习研究笔记 关注 机器学习系统，深度学习， LLVM，性能剖视， Linux操作系统内核 话题 关注 C/C++. JAVA. Python. Golang. Chisel. 编程语言话题 ( Writing Blogs using …
  ☆78Updated 5 years ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆150Updated 2 years ago
• sycuricon / starship
  Run rocket-chip on FPGA
  ☆76Updated last month
• YanB25 / Tomasulo
  An out-of-order execution algorithm for pipeline CPU, implemented by verilog
  ☆42Updated 7 years ago
• cnrv / fpga-rocket-chip
  Wrapper for Rocket-Chip on FPGAs
  ☆138Updated 3 years ago
• schoeberl / chisel-lab
  Lab exercises for Chisel in the digital electronics 2 course at DTU
  ☆217Updated last month
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆221Updated 5 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆108Updated 4 years ago
• jasonlin316 / RISC-V-CPU
  A RISC-V 5-stage pipelined CPU that supports vector instructions. Tape-out with U18 technology.
  ☆141Updated 6 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆165Updated this week
• schoeberl / chisel-examples
  Chisel examples and code snippets
  ☆263Updated 3 years ago
• grantae / OpenMIPS
  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions,…
  ☆82Updated 6 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆189Updated 2 months ago
• z4yx / NaiveMIPS-HDL
  Naïve MIPS32 SoC implementation
  ☆118Updated 5 years ago
• SimpleCPU / SimpleCPU
  An open source CPU design and verification platform for academia
  ☆113Updated 3 months ago
• zslwyuan / Basic-SIMD-Processor-Verilog-Tutorial
  Implementation of a simple SIMD processor in Verilog, core of which is a 16-bit SIMD ALU. 2's compliment calculations are implemented in …
  ☆142Updated 3 years ago
• watz0n / learn-rv32i-asap
  A Simple As Possible RISCV-32I core with debug module.
  ☆42Updated 6 years ago
• SpinalHDL / SpinalWorkshop
  Labs to learn SpinalHDL
  ☆151Updated last year
• OpenXiangShan / xs-env
  XiangShan Frontend Develop Environment
  ☆68Updated 2 weeks ago
• Intensivate / learning-journey
  Chisel Learning Journey
  ☆111Updated 2 years ago
• danshanley / FPU
  IEEE 754 floating point unit in Verilog
  ☆150Updated 9 years ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆168Updated 5 years ago
• ucb-bar / berkeley-hardfloat
  ☆359Updated 3 months ago
• lowRISC / ariane
  Ariane is a 6-stage RISC-V CPU
  ☆151Updated 6 years ago
• lingscale / cc01
  ☆30Updated 9 months ago