Alternatives and similar repositories for OpenMIPS:

Users that are interested in OpenMIPS are comparing it to the libraries listed below

• lowRISC / riscv-compliance
  TEMPORARY FORK of the riscv-compliance repository
  ☆26Updated 4 years ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆82Updated 4 years ago
• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆235Updated 6 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆212Updated 4 years ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆153Updated last week
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆193Updated 10 months ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆91Updated last week
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆279Updated last year
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆142Updated this week
• merledu / nucleusrv
  NucleusRV - A 32-bit 5 staged pipelined risc-v core.
  ☆66Updated 3 weeks ago
• XUANTIE-RV / opene906
  OpenXuantie - OpenE906 Core
  ☆138Updated 10 months ago
• chsasank / ARM7
  Implemetation of pipelined ARM7TDMI processor in Verilog
  ☆89Updated 7 years ago
• chipsalliance / rocket-tools
  Software tools that support rocket-chip (GNU toolchain, ISA simulator, tests)
  ☆54Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆98Updated last month
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆145Updated 6 months ago
• leros-dev / leros
  A Tiny Processor Core
  ☆108Updated 2 months ago
• OpenXiangShan / HuanCun
  Open-source high-performance non-blocking cache
  ☆80Updated 2 weeks ago
• cassuto / nano-cpu32k
  Linux-capable superscalar out-of-order RISC core (with Cache& MMU) and SoC, having been verified on Xilinx Kintex-7 FPGA.
  ☆54Updated 8 months ago
• chipsalliance / riscv-vector-tests
  Unit tests generator for RVV 1.0
  ☆83Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆229Updated 5 months ago
• SpinalHDL / NaxRiscv
  ☆283Updated 2 months ago
• YosysHQ / riscv-formal
  RISC-V Formal Verification Framework
  ☆137Updated this week
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆149Updated this week
• OSCPU / ysyxSoC
  ☆86Updated last week
• pulp-platform / pulp-runtime
  Simple runtime for Pulp platforms
  ☆47Updated last month
• riscvarchive / riscv-code-size-reduction
  ☆150Updated last year
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆144Updated last year
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆149Updated 2 years ago
• OpenXiangShan / XS-Verilog-Library
  ☆41Updated 3 years ago
• iammituraj / pequeno_riscv
  Pequeno (PQR5) is a 5-stage pipelined in-order RISC-V CPU Core compliant with RV32I ISA.
  ☆86Updated 2 weeks ago