Alternatives and similar repositories for OpenMIPS

Users that are interested in OpenMIPS are comparing it to the libraries listed below

• openhwgroup / cv32e40x
  4 stage, in-order, compute RISC-V core based on the CV32E40P
  ☆244Updated 9 months ago
• SpinalHDL / VexiiRiscv
  Like VexRiscv, but, Harder, Better, Faster, Stronger
  ☆169Updated 3 weeks ago
• openhwgroup / cv32e40s
  4 stage, in-order, secure RISC-V core based on the CV32E40P
  ☆150Updated 9 months ago
• risclite / SuperScalar-RISCV-CPU
  SSRV(Super-Scalar RISC-V) --- Super-scalar out-of-order RV32IMC CPU core, 6.4 CoreMark/MHz.
  ☆217Updated 5 years ago
• tilk / riscv-simple-sv
  A simple RISC V core for teaching
  ☆193Updated 3 years ago
• lowRISC / muntjac
  64-bit multicore Linux-capable RISC-V processor
  ☆95Updated 3 months ago
• ucb-bar / riscv-torture
  RISC-V Torture Test
  ☆197Updated last year
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆155Updated 3 years ago
• SpinalHDL / NaxRiscv
  ☆293Updated 2 weeks ago
• riscv-non-isa / riscv-trace-spec
  RISC-V Processor Trace Specification
  ☆192Updated 3 weeks ago
• RoaLogic / RV12
  RISC-V CPU Core
  ☆369Updated 2 months ago
• ucb-bar / saturn-vectors
  Chisel RISC-V Vector 1.0 Implementation
  ☆108Updated 3 months ago
• openhwgroup / force-riscv
  Instruction Set Generator initially contributed by Futurewei
  ☆292Updated last year
• leros-dev / leros
  A Tiny Processor Core
  ☆110Updated last month
• OpenXiangShan / fudian
  Open source high performance IEEE-754 floating unit
  ☆83Updated last year
• openhwgroup / cva5
  The CORE-V CVA5 is an Application class 5-stage RISC-V CPU specifically targetting FPGA implementations.
  ☆119Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆230Updated 9 months ago
• risclite / ARM9-compatible-soft-CPU-core
  This ARMv4-compatible CPU core is written in synthesiable verilog.It could launch uCLinux and Linux in MODELSIM. It has high Dhrystone be…
  ☆89Updated 4 years ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆274Updated this week
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆150Updated last year
• lowRISC / riscv-compliance
  TEMPORARY FORK of the riscv-compliance repository
  ☆29Updated 4 years ago
• rafaelcalcada / rvx
  RISC-V microcontroller IP core developed in Verilog
  ☆178Updated 4 months ago
• ultraembedded / exactstep
  Instruction set simulator for RISC-V, MIPS and ARM-v6m
  ☆101Updated 3 years ago
• merledu / nucleusrv
  NucleusRV (rv32-imf) - A 32-bit 5 staged pipelined risc-v core.
  ☆73Updated last week
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆160Updated 5 years ago
• OpenXiangShan / difftest
  Modern co-simulation framework for RISC-V CPUs
  ☆148Updated last week
• riscvarchive / riscv-code-size-reduction
  ☆149Updated last year
• pulp-platform / riscv-dbg
  RISC-V Debug Support for our PULP RISC-V Cores
  ☆266Updated 4 months ago
• jlpteaching / dinocpu
  A teaching-focused RISC-V CPU design used at UC Davis
  ☆150Updated 2 years ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆174Updated last month