Alternatives and similar repositories for spi-master

Users that are interested in spi-master are comparing it to the libraries listed below

• nandland / spi-slave
  SPI Slave for FPGA in Verilog and VHDL
  ☆218Updated last year
• alexforencich / verilog-uart
  Verilog UART
  ☆517Updated 10 months ago
• jamieiles / uart
  Verilog UART
  ☆187Updated 12 years ago
• alexforencich / verilog-i2c
  Verilog I2C interface for FPGA implementation
  ☆665Updated 10 months ago
• ultraembedded / core_ddr3_controller
  A DDR3 memory controller in Verilog for various FPGAs
  ☆542Updated 4 years ago
• dpretet / async_fifo
  A dual clock asynchronous FIFO written in verilog, tested with Icarus Verilog
  ☆402Updated 3 months ago
• lekgolo167 / enxor-logic-analyzer
  FPGA Logic Analyzer and GUI
  ☆145Updated 3 years ago
• benreynwar / fft-dit-fpga
  Verilog module for calculation of FFT.
  ☆190Updated 13 years ago
• ultraembedded / cores
  Various HDL (Verilog) IP Cores
  ☆857Updated 4 years ago
• stffrdhrn / sdram-controller
  Verilog SDRAM memory controller
  ☆351Updated 8 years ago
• alexforencich / verilog-lfsr
  Fully parametrizable combinatorial parallel LFSR/CRC module
  ☆159Updated 10 months ago
• csus-senior-design / i2c
  I2C Master and Slave
  ☆38Updated 10 years ago
• dirjud / Nitro-Parts-lib-SPI
  Verilog SPI master and slave
  ☆62Updated 9 years ago
• nanamake / r22sdf
  Pipeline FFT Implementation in Verilog HDL
  ☆152Updated 6 years ago
• ZipCPU / sdspi
  SD-Card controller, using either SPI, SDIO, or eMMC interfaces
  ☆341Updated 2 months ago
• WangXuan95 / FPGA-UART
  This repo includes 3 independent modules: UART receiver, UART transmitter, UART to AXI4 master. 本项目包含3个独立模块：UART接收器、UART发送器、UART转AXI4交互式调…
  ☆279Updated 2 years ago
• efabless / raven-picorv32
  Silicon-validated SoC implementation of the PicoSoc/PicoRV32
  ☆279Updated 5 years ago
• ben-marshall / uart
  A simple implementation of a UART modem in Verilog.
  ☆168Updated 4 years ago
• alexforencich / cocotbext-axi
  AXI interface modules for Cocotb
  ☆304Updated 2 months ago
• avakar / usbcorev
  A full-speed device-side USB peripheral core written in Verilog.
  ☆235Updated 3 years ago
• alexforencich / verilog-dsp
  Verilog digital signal processing components
  ☆162Updated 3 years ago
• ZipCPU / wbuart32
  A simple, basic, formally verified UART controller
  ☆319Updated last year
• NXP / i3c-slave-design
  MIPI I3C Basic v1.0 communication Slave source code in Verilog with BSD license to support use in sensors and other devices.
  ☆132Updated 5 years ago
• suisuisi / FPGA_Library
  Vivado诸多IP，包括图像处理等
  ☆234Updated last year
• ZipCPU / wb2axip
  Bus bridges and other odds and ends
  ☆613Updated 8 months ago
• freecores / verilog_fixed_point_math_library
  Fixed Point Math Library for Verilog
  ☆145Updated 11 years ago
• ultraembedded / riscv_soc
  Basic RISC-V Test SoC
  ☆162Updated 6 years ago
• cjhonlyone / picorv32_Xilinx
  A picorv32-riscv Soc with DMAC and Ethernet controller & lwip & Kirtex7@333MHz
  ☆77Updated 4 years ago
• AngeloJacobo / UberDDR3
  Opensource DDR3 Controller
  ☆402Updated this week
• jakubcabal / spi-fpga
  SPI master and SPI slave for FPGA written in VHDL
  ☆180Updated 4 years ago