VHDL Modules
☆24Mar 16, 2015Updated 11 years ago
Alternatives and similar repositories for VHDL_Modules
Users that are interested in VHDL_Modules are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- ☆18Sep 16, 2020Updated 5 years ago
- Blink demo for GOWIN FPGA dev kit DK-START-GW1N4☆12Oct 8, 2018Updated 7 years ago
- High level Data Link Layer Control (HDLC) Protocol (16 bit) implementation using VHDL hardware description language.☆31Dec 1, 2016Updated 9 years ago
- A C++ template library for FPGAs on top of Xilinx Vivado HLS☆14Feb 2, 2017Updated 9 years ago
- IP Cores that can be used within Vivado☆27May 18, 2021Updated 5 years ago
- 1-Click AI Models by DigitalOcean Gradient • AdDeploy popular AI models on DigitalOcean Gradient GPU virtual machines with just a single click. Zero configuration with optimized deployments.
- Portable HyperRAM controller☆69Dec 8, 2024Updated last year
- SPI-Flash XIP Interface (Verilog)☆50Oct 24, 2021Updated 4 years ago
- A Javascript library for generating blocks for the ICEstudio FPGA development environment☆10Jul 31, 2018Updated 7 years ago
- FPGA Portable Music Generator☆11Aug 1, 2018Updated 7 years ago
- VHDL Code for infrastructural blocks (designed for FPGA)☆15Oct 26, 2022Updated 3 years ago
- ☆10May 26, 2023Updated 3 years ago
- This IP provides a bridge between UART signals and the Advanced Microcontroller Bus Architecture (AMBA®) AXI4 Lite interface.☆25Nov 7, 2018Updated 7 years ago
- 控制组生存指南☆10Jun 28, 2019Updated 7 years ago
- ☆26Jun 7, 2020Updated 6 years ago
- Deploy to Railway using AI coding agents - Free Credits Offer • AdUse Claude Code, Codex, OpenCode, and more. Autonomous software development now has the infrastructure to match with Railway.
- SwapForth J1a processor for Icestudio☆12Aug 28, 2020Updated 5 years ago
- Colecciones para el tutorial Electrónica digital para Makers con FPGAs Libres☆11Dec 4, 2018Updated 7 years ago
- ☆10Feb 3, 2017Updated 9 years ago
- Very simple Cortex-M1 SoC design based on ARM DesignStart☆18Jan 25, 2022Updated 4 years ago
- Repository for showcasing DevOps practices within microcontroller projects☆12May 16, 2026Updated last month
- Example Projects for the Microsemi SmartFusion 2☆11Dec 10, 2017Updated 8 years ago
- Blackfin CPU support for ghidra☆27Aug 10, 2024Updated last year
- Gaussian noise generator Verilog IP core☆34Updated this week
- ☆14Mar 12, 2021Updated 5 years ago
- Managed Database hosting by DigitalOcean • AdPostgreSQL, MySQL, MongoDB, Kafka, Valkey, and OpenSearch available. Automatically scale up storage and focus on building your apps.
- Open-source high performance AXI4-based HyperRAM memory controller☆88Oct 6, 2022Updated 3 years ago
- Library of VHDL components that are useful in larger designs.☆245Oct 10, 2023Updated 2 years ago
- SystemVerilog examples for a digital design course☆14Mar 30, 2021Updated 5 years ago
- ☆17Jul 12, 2020Updated 5 years ago
- ☆20Jun 18, 2022Updated 4 years ago
- powerpc processor prototype and an example of semiconductor startup biz plan☆14Feb 2, 2019Updated 7 years ago
- Wi-Fi LDPC codec Verilog IP core☆19Jun 30, 2026Updated last week
- verilog example to drive PCM5102 DAC with FPGA☆19Apr 30, 2018Updated 8 years ago
- A printed circuit board representation of the Fairchild μL914 dual-input NOR gate☆18May 22, 2019Updated 7 years ago
- GPUs on demand by Runpod - Special Offer Available • AdRun AI, ML, and HPC workloads on powerful cloud GPUs—without limits or wasted spend. Deploy GPUs in under a minute and pay by the second.
- Control your miLights iBox2 V6 with Domoticz☆11Jan 8, 2017Updated 9 years ago
- C128 80 column screen editor☆11Feb 28, 2024Updated 2 years ago
- Arduino firmware to provide USB host functionality using MAX3421E USB host controller☆26Aug 14, 2016Updated 9 years ago
- ☆13Nov 9, 2023Updated 2 years ago
- How to generate NTSC compliant(?) composite color video with an FPGA☆45Apr 26, 2020Updated 6 years ago
- core files for the MiST fpga☆33Nov 22, 2024Updated last year
- Nirah is a project aimed at automatically wrapping verilator C++ models in python in order for high level, extendable control and verific…☆12Mar 6, 2019Updated 7 years ago