Alternatives and similar repositories for VHDL_Modules:

Users that are interested in VHDL_Modules are comparing it to the libraries listed below

• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆32Updated this week
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆56Updated last year
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆58Updated 2 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆45Updated 2 months ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• Cognoscan / BoostDSP
  VHDL Library for implementing common DSP functionality.
  ☆27Updated 6 years ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆94Updated 2 months ago
• tirfil / VhdI2CSlave
  I2C Slave Interface (Vhdl)
  ☆22Updated 2 years ago
• ZipCPU / qspiflash
  A set of Wishbone Controlled SPI Flash Controllers
  ☆79Updated 2 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆25Updated 4 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆40Updated 6 years ago
• emard / flearadio
  Digital FM Radio Receiver for FPGA
  ☆60Updated 9 years ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆30Updated 3 years ago
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆59Updated 2 years ago
• ultraembedded / minispartan6-audio
  miniSpartan6+ (Spartan6) FPGA based MP3 Player
  ☆27Updated 5 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆100Updated last year
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆35Updated 3 years ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆108Updated 3 years ago
• ultraembedded / core_audio
  Audio controller (I2S, SPDIF, DAC)
  ☆82Updated 5 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆40Updated 3 weeks ago
• esynr3z / proto245
  🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)
  ☆35Updated 3 years ago
• enclustra / en_cl_fix
  Fixed-point math library with VHDL, Python and MATLAB support
  ☆18Updated 5 months ago
• hdlguy / make_for_vivado
  experimentation with gnu make for Xilinx Vivado compilation. dependencies can be complicated.
  ☆22Updated last year
• hamsternz / second_order_sigma_delta_DAC
  A comparison of 1st and 2nd order sigma delta DAC for FPGA
  ☆55Updated 4 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆31Updated 3 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆78Updated 4 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆34Updated 7 years ago