Alternatives and similar repositories for VHDL_Modules

Users that are interested in VHDL_Modules are comparing it to the libraries listed below

• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆35Updated 4 years ago
• ZipCPU / interpolation
  Digital Interpolation Techniques Applied to Digital Signal Processing
  ☆64Updated last year
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆53Updated 10 months ago
• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆46Updated 5 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆30Updated 6 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆64Updated 2 years ago
• ultraembedded / core_usb_cdc
  Basic USB-CDC device core (Verilog)
  ☆80Updated 4 years ago
• ZipCPU / cordic
  A series of CORDIC related projects
  ☆115Updated 10 months ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆110Updated last year
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆32Updated 8 years ago
• ultraembedded / core_audio
  Audio controller (I2S, SPDIF, DAC)
  ☆89Updated 6 years ago
• ultraembedded / core_spiflash
  SPI-Flash XIP Interface (Verilog)
  ☆45Updated 3 years ago
• tirfil / VhdI2CSlave
  I2C Slave Interface (Vhdl)
  ☆25Updated 3 years ago
• ultraembedded / core_ulpi_wrapper
  ULPI Link Wrapper (USB Phy Interface)
  ☆29Updated 5 years ago
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆74Updated 3 years ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆17Updated 2 years ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆120Updated 4 years ago
• hukenovs / intfftk
  Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…
  ☆87Updated 2 years ago
• 0xArt / Tiny_But_Mighty_I2C_Master_Verilog
  I2C Master Verilog module
  ☆34Updated 4 months ago
• ZipCPU / dspfilters
  A collection of demonstration digital filters
  ☆156Updated last year
• nandland / memory
  Single Port RAM, Dual Port RAM, FIFO
  ☆27Updated 3 years ago
• ultraembedded / core_dvi_framebuffer
  Minimal DVI / HDMI Framebuffer
  ☆82Updated 5 years ago
• freecores / ethmac
  Ethernet MAC 10/100 Mbps
  ☆84Updated 6 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆44Updated 3 years ago
• paulscherrerinstitute / psi_common
  Common elements for FPGA Design (FIFOs, RAMs, etc.)
  ☆34Updated 7 months ago
• dawsonjon / FPGA-radio
  Software Defined Radio in FPGA uses LVDS IO pins as 1-bit ADC
  ☆110Updated 8 years ago
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆61Updated 2 years ago
• Elrori / Delta-sigma-ADC-verilog
  Delta-sigma ADC,PDM audio FPGA Implementation
  ☆72Updated 3 years ago
• CospanDesign / nysa-verilog
  Verilog Repository for GIT
  ☆33Updated 4 years ago
• Cognoscan / VerilogCogs
  Verilog Modules for DSP functions and other common tasks to make FPGA development easier and more fun.
  ☆20Updated 10 years ago