DiegoRosales / VHDL_Modules

Related projects ⓘ

Alternatives and complementary repositories for VHDL_Modules

• ultraembedded / core_usb_fs_phy
  USB Full Speed PHY
  ☆39Updated 4 years ago
• ZipCPU / wbi2c
  Wishbone controlled I2C controllers
  ☆44Updated last week
• alexforencich / xfcp
  Extensible FPGA control platform
  ☆54Updated last year
• tirfil / VhdI2CSlave
  I2C Slave Interface (Vhdl)
  ☆20Updated 2 years ago
• Cognoscan / BoostDSP
  VHDL Library for implementing common DSP functionality.
  ☆27Updated 6 years ago
• olofk / wb_intercon
  Wishbone interconnect utilities
  ☆37Updated 6 months ago
• fcayci / vhdl-axis-uart
  UART to AXI Stream interface written in VHDL
  ☆16Updated 2 years ago
• owocomm-0 / fpga-fft
  A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm
  ☆106Updated 3 years ago
• BBN-Q / VHDL-JESD204b
  JESD204b modules in VHDL
  ☆29Updated 5 years ago
• ultraembedded / core_ftdi_bridge
  FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge
  ☆28Updated 3 years ago
• Architech-Silica / Designing-a-Custom-AXI-Master-using-BFMs
  A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models
  ☆32Updated 6 years ago
• ultraembedded / core_audio
  Audio controller (I2S, SPDIF, DAC)
  ☆80Updated 5 years ago
• sergachev / spi_mem_programmer
  Small (Q)SPI flash memory programmer in Verilog
  ☆55Updated 2 years ago
• ultraembedded / core_usb_host
  Basic USB 1.1 Host Controller for small FPGAs
  ☆85Updated 4 years ago
• FMCHUB / Lib_Altium
  Altium Designer libraries for ANSI/VITA 57 FPGA Mezzanine Card (FMC) Standard
  ☆42Updated 2 years ago
• MorrisMA / 1PPS-DPLL
  DPLL for phase-locking to 1PPS signal
  ☆28Updated 8 years ago
• davemuscle / sigma_delta_converters
  Implementation and test of reusable sigma-delta A/D converters written in SystemVerilog on a MAX10 FPGA with minimal external components
  ☆55Updated 2 years ago
• enjoy-digital / litejesd204b
  Small footprint and configurable JESD204B core
  ☆40Updated last month
• m-labs / jesd204b
  JESD204B core for Migen/MiSoC
  ☆36Updated 3 years ago
• magro732 / OpenRIO
  Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.
  ☆34Updated 7 years ago
• gtjennings1 / UPDuino-LH154Q01-Display
  Design to connect Lattice Ultraplus FPGA to LH154Q01 Display
  ☆28Updated 6 years ago
• nandland / memory
  Single Port RAM, Dual Port RAM, FIFO
  ☆20Updated 2 years ago
• hamsternz / second_order_sigma_delta_DAC
  A comparison of 1st and 2nd order sigma delta DAC for FPGA
  ☆52Updated 3 years ago
• no2fpga / no2usb
  Nitro USB FPGA core
  ☆83Updated 8 months ago
• Architech-Silica / Designing-a-Custom-AXI-Slave-Peripheral
  A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools
  ☆39Updated 6 years ago
• esynr3z / proto245
  🔴 SystemVerilog FPGA cores to communicate with FTDI Synchronous/Asynchronous FIFOs (FT245 protocol)
  ☆34Updated 3 years ago
• ZipCPU / dpll
  A collection of phase locked loop (PLL) related projects
  ☆99Updated 10 months ago
• skristiansson / i2s
  i2s core, with support for both transmit and receive
  ☆28Updated 6 years ago
• viktor-nikolov / MicroBlaze-DDR3-tutorial
  Tutorial of a HW design of MicroBlaze using DDR3 RAM on Arty A7 board; DDR3 RAM speed test application
  ☆30Updated 5 months ago
• www-asics-ws / usb2_dev
  USB 2.0 Device IP Core
  ☆52Updated 7 years ago