DiegoRosales / VHDL_ModulesLinks
VHDL Modules
☆24Updated 10 years ago
Alternatives and similar repositories for VHDL_Modules
Users that are interested in VHDL_Modules are comparing it to the libraries listed below
Sorting:
- Common elements for FPGA Design (FIFOs, RAMs, etc.)☆33Updated 4 months ago
- VHDL Library for implementing common DSP functionality.☆29Updated 6 years ago
- Single Port RAM, Dual Port RAM, FIFO☆24Updated 3 years ago
- USB Full Speed PHY☆44Updated 5 years ago
- Wishbone controlled I2C controllers☆50Updated 7 months ago
- ULPI Link Wrapper (USB Phy Interface)☆28Updated 5 years ago
- Extensible FPGA control platform☆62Updated 2 years ago
- A demonstration showing how several components can be compsed to build a simulated spectrogram☆46Updated last year
- DPLL for phase-locking to 1PPS signal☆32Updated 8 years ago
- A comparison of 1st and 2nd order sigma delta DAC for FPGA☆58Updated 4 years ago
- FTDI FT245 Style Synchronous/Asynchronous FIFO Bridge☆32Updated 4 years ago
- Collection of all FPGA related PSI libraries in the correct folder strucutre. Each library is included as submodule.☆36Updated last year
- miniSpartan6+ (Spartan6) FPGA based MP3 Player☆27Updated 5 years ago
- I2C Slave Interface (Vhdl)☆24Updated 3 years ago
- Small (Q)SPI flash memory programmer in Verilog☆63Updated 2 years ago
- A guide to creating custom AXI-lite slave peripherals using the Xilinx Vivado tools☆40Updated 7 years ago
- i2s core, with support for both transmit and receive☆30Updated 7 years ago
- Basic USB 1.1 Host Controller for small FPGAs☆90Updated 5 years ago
- JESD204b modules in VHDL☆30Updated 6 years ago
- Wishbone interconnect utilities☆41Updated 4 months ago
- ☆32Updated 2 years ago
- A set of Wishbone Controlled SPI Flash Controllers☆82Updated 2 years ago
- A guide to creating custom AXI4 masters using the Xilinx Vivado tools and Bus Functional Models☆34Updated 7 years ago
- Fully pipelined Integer Scaled / Unscaled Radix-2 Forward/Inverse Fast Fourier Transform (FFT) IP-core for newest Xilinx FPGAs (Source la…☆88Updated 2 years ago
- A highly optimized streaming FFT core based on Bailey's 4-step large FFT algorithm☆114Updated 4 years ago
- A collection of phase locked loop (PLL) related projects☆106Updated last year
- Contains VHDL IP-blocks to create stand-alone RapidIO-endpoints, RapidIO-switches and RapidIO-switches with local endpoints.☆33Updated 8 years ago
- Ethernet MAC 10/100 Mbps☆83Updated 5 years ago
- Verilog IP Cores & Tests☆13Updated 7 years ago
- Digital FM Radio Receiver for FPGA☆61Updated 9 years ago