Alternatives and similar repositories for uciedigital:

Users that are interested in uciedigital are comparing it to the libraries listed below

• amonemi / ProNoC
  Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
  ☆52Updated last week
• sifferman / labs-with-cva6
  Advanced Architecture Labs with CVA6
  ☆54Updated last year
• ananthbhat94 / DDR4MemoryController
  HDL code for a DDR4 memory controller implementing an Open Page Policy and Out of Order execution.
  ☆73Updated 7 years ago
• ccelio / chisel-style-guide
  A Style Guide for the Chisel Hardware Construction Language
  ☆107Updated 3 years ago
• ucb-bar / constellation
  A Chisel RTL generator for network-on-chip interconnects
  ☆186Updated last week
• kuladeepsaireddy / OpenNoc
  ☆31Updated 5 years ago
• aignacio / axi_dma
  General Purpose AXI Direct Memory Access
  ☆49Updated 10 months ago
• openhwgroup / cv-hpdcache
  RTL sources of the High-Performance L1 Dcache (HPDcache) for OpenHW CV cores
  ☆68Updated last week
• ic-lab-duth / RISC-V-Vector
  Vector processor for RISC-V vector ISA
  ☆116Updated 4 years ago
• ic-lab-duth / NoCpad
  HLS for Networks-on-Chip
  ☆33Updated 4 years ago
• Chainsaw-Team / Chainsaw
  a hardware design library based on SpinalHDL, especially for stream processing operators on Xilinx FPGAs for Arithmetic, DSP, Communicati…
  ☆59Updated last year
• stillwater-sc / RISC-V-TensorCore
  Transactional Verilog design and Verilator Testbench for a RISC-V TensorCore Vector co-processor for reproducible linear algebra
  ☆51Updated 3 years ago
• pulp-platform / fpu
  ☆41Updated 6 years ago
• anan-cn / Open-Source-Network-on-Chip-Router-RTL
  ☆71Updated 10 years ago
• dpretet / axi-crossbar
  An AXI4 crossbar implementation in SystemVerilog
  ☆137Updated last month
• bakhshalipour / NoC-Verilog
  A verilog implementation for Network-on-Chip
  ☆73Updated 7 years ago
• mmxsrup / axi4-interface
  AXI4 and AXI4-Lite interface definitions
  ☆93Updated 4 years ago
• oprecomp / DDR4_controller
  ☆53Updated 4 years ago
• chiselverify / chiselverify
  A dynamic verification library for Chisel.
  ☆146Updated 4 months ago
• pulp-platform / common_verification
  SystemVerilog modules and classes commonly used for verification
  ☆46Updated 2 months ago
• pulp-platform / iDMA
  A modular, parametrizable, and highly flexible Data Movement Accelerator (DMA)
  ☆137Updated 2 weeks ago
• freecores / round_robin_arbiter
  round robin arbiter
  ☆70Updated 10 years ago
• seldridge / rocket-rocc-examples
  Tests for example Rocket Custom Coprocessors
  ☆73Updated 5 years ago
• chipsalliance / uvm-verilator
  ☆88Updated last year
• cnrv / CNRV-FPU
  Basic floating-point components for RISC-V processors
  ☆65Updated 5 years ago
• aignacio / ravenoc
  RaveNoC is a configurable HDL NoC (Network-On-Chip) suitable for MPSoCs and different MP applications
  ☆163Updated 4 months ago
• Arteris-IP / tlm2-interfaces
  contains TLM2 based interfaces for AXI, ACE, CHI and other standard protocols
  ☆56Updated last month
• taichi-ishitani / tnoc
  Network on Chip Implementation written in SytemVerilog
  ☆171Updated 2 years ago
• rgb000000 / eyeriss-chisel3
  eyeriss-chisel3
  ☆40Updated 2 years ago
• pulp-platform / FlooNoC
  A Fast, Low-Overhead On-chip Network
  ☆182Updated this week