☆13Jun 8, 2026Updated 4 months ago
Alternatives and similar repositories for OpenRTLSet
Users that are interested in OpenRTLSet are comparing it to the libraries listed below. We may earn a commission when you buy through links labeled 'Ad' on this page.
Sorting:
- TuRTLe: A Unified Evaluation of LLMs for RTL Generation 🐢 (MLCAD 2025, ACM TODAES 2026)☆53Jul 22, 2026Updated 3 months ago
- 🧩 Starter template for ASIC hardware IP blocks with Vyges metadata, OpenLane integration, and comprehensive documentation☆13Apr 30, 2026Updated 6 months ago
- Template Verilator project for beginners☆13Feb 2, 2023Updated 3 years ago
- Fabric generator and CAD tools graphical frontend☆19Oct 6, 2026Updated 3 weeks ago
- The SoC for the introduction to chip design course spring 2026☆21May 22, 2026Updated 5 months ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- HeiChips 2026 LibreLane Workshop☆16Aug 7, 2026Updated 2 months ago
- Replace Tcl scripting with Python☆18Aug 25, 2026Updated 2 months ago
- Verilog Generation with Reinforcement Learning☆12Jul 15, 2025Updated last year
- PyCacheGen: A Highly Configurable Open-Source Generator for Synthesizable Caches☆18Dec 14, 2025Updated 10 months ago
- ☆16May 24, 2025Updated last year
- An open silicon CHERIoT Ibex microcontroller chip☆19May 23, 2025Updated last year
- RISC-V IOMMU in verilog☆22Jun 18, 2022Updated 4 years ago
- PRO-V: An Efficient Program Generation Multi-Agent System for Automatic RTL Verification☆36Dec 11, 2025Updated 10 months ago
- ☆15Oct 9, 2026Updated 3 weeks ago
- Proton VPN Special Offer - Get 70% off • AdSpecial partner offer. Trusted by over 100 million users worldwide. Tested, Approved and Recommended by Experts.
- Magma Hackathon☆12Mar 4, 2020Updated 6 years ago
- AI-native IC design plugin with MCP-EDA — from natural-language intent to verified silicon.☆28Updated this week
- The Common Evaluation Platform (CEP), based on UCB's Chipyard Framework, is an SoC design that contains only license-unencumbered, freely…☆26Sep 26, 2024Updated 2 years ago
- A series of mainstream machine learning algorithms implement on FPGA.☆15Sep 1, 2021Updated 5 years ago
- LLM4HWDesign Starting Toolkit☆20Oct 4, 2024Updated 2 years ago
- K210芯片的裸机编程代码使用案例,供学习使用,使用的是亚博智能的K210开发板套件(不是打广告哈)(在design_maix中已经支持了maix bit和maixduino开发板)。☆12Feb 16, 2021Updated 5 years ago
- Don't memorize 500 tools — describe the chip outcome you want. Open FPGA skill pack (timing closure, CDC audit, full flow, Zynq bring-up……☆22Jun 9, 2026Updated 4 months ago
- A Formal Verification Methodology to lower the adoption barriers for Formal Verification of ASIC and FPGA designs in the Space sector (th…☆25Jun 29, 2026Updated 4 months ago
- Build infrastructure for class-wide tapeout for 18-224/624 Intro to Open Source Chip Design, Spring 2023☆24Aug 10, 2023Updated 3 years ago
- AI Agents on DigitalOcean Gradient AI Platform • AdBuild production-ready AI agents using customizable tools or access multiple LLMs through a single endpoint. Create custom knowledge bases or connect external data.
- EE 272B - VLSI Design Project☆15Jun 24, 2021Updated 5 years ago
- Project where we conceptualized and designed a simple neural network accelerator, loosely based on the Eyeriss architecture, to accelerat…☆11Dec 13, 2019Updated 6 years ago
- 高性价比人生指南:650 条建议,34 个主题。省钱、避坑、少走弯路。场景导航、章节阅读、全文检索、关系图、收藏、PDF 与 Obsidian 下载。☆43Oct 12, 2026Updated 2 weeks ago
- ☆10Dec 19, 2022Updated 3 years ago
- An open framework for designing and deploying custom AI-driven HW/SW co-design flows fast☆117Updated this week
- ☆30Jul 27, 2017Updated 9 years ago
- ☆10Aug 1, 2025Updated last year
- 10GbE XGMII TCP/IPv4 packet generator in C, co-simulating with Verilog, SystemVerilog and VHDL☆29Jan 28, 2025Updated last year
- ☆20Aug 8, 2024Updated 2 years ago
- Deploy on Railway without the complexity - Free Credits Offer • AdConnect your repo and Railway handles the rest with instant previews. Quickly provision container image services, databases, and storage volumes.
- ☆15Apr 28, 2026Updated 6 months ago
- LintLLM is an open-source Verilog linting framework powered by Large Language Models (LLMs).☆12Aug 14, 2026Updated 2 months ago
- ☆14Jan 21, 2025Updated last year
- ☆18Dec 15, 2025Updated 10 months ago
- Code and data release for FEABench: Evaluating Language Models on Multiphysics Reasoning Ability. [MATH-AI workshop, NeurIPS 2024]☆14May 7, 2025Updated last year
- MCP Server for Agent Skill Ninja - Search, Install, and Manage Agent Skills☆12May 20, 2026Updated 5 months ago
- Research project from UCI's AICPS lab: using GNNs to enable hardware security and prevent hardware trojans☆10Mar 31, 2021Updated 5 years ago