An open-source, JEDEC JESD270-4A-compliant HBM4 memory subsystem (controller + PHY-shim + DFT + RAS + security wrapper) tightly coupled to an open RISC-V-native LPU accelerator. Apache-2.0 RTL, CERN-OHL-W-2.0 analog/GDSII, trademark-controlled compatibility certification.
☆26Jun 14, 2026Updated 4 months ago
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