ucb-bar / berkeley-softfloat-3

Related projects ⓘ

Alternatives and complementary repositories for berkeley-softfloat-3

• lowRISC / riscv-llvm
  RISC-V support for LLVM projects (LLVM, Clang, ...)
  ☆253Updated 3 months ago
• riscv-non-isa / riscv-toolchain-conventions
  Documenting the expected behaviour and supported command-line switches for GNU and LLVM based RISC-V toolchains
  ☆144Updated 2 months ago
• bucaps / marss-riscv
  TinyEMU based full system cycle-level micro-architectural research simulator for single-core RISC-V systems
  ☆144Updated 2 years ago
• michaeljclark / rv8
  RISC-V simulator for x86-64
  ☆680Updated 2 years ago
• riscvarchive / riscv-code-size-reduction
  ☆150Updated 8 months ago
• riscv / riscv-bitmanip
  Working draft of the proposed RISC-V Bitmanipulation extension
  ☆204Updated 7 months ago
• frasercrmck / llvm-leg
  ☆107Updated 3 years ago
• riscv-non-isa / riscv-c-api-doc
  Documentation of the RISC-V C API
  ☆74Updated this week
• riscv / riscv-j-extension
  Working Draft of the RISC-V J Extension Specification
  ☆167Updated 3 weeks ago
• michaeljclark / riscv-probe
  Simple machine mode program to probe RISC-V control and status registers
  ☆116Updated last year
• ucb-bar / esp-llvm
  UCB-BAR fork of LLVM! NOT UPSTREAM RISCV LLVM
  ☆123Updated 3 years ago
• pulp-platform / snitch
  ⛔ DEPRECATED ⛔ Lean but mean RISC-V system!
  ☆218Updated 11 months ago
• riscv / sail-riscv
  Sail RISC-V model
  ☆459Updated this week
• sifive / riscv-llvm
  SiFive's LLVM working tree
  ☆83Updated 3 months ago
• riscv / riscv-fast-interrupt
  Proposal for a RISC-V Core-Local Interrupt Controller (CLIC)
  ☆245Updated this week
• riscv / riscv-p-spec
  RISC-V Packed SIMD Extension
  ☆141Updated last year
• riscv-software-src / riscv-pk
  RISC-V Proxy Kernel
  ☆592Updated last month
• chipsalliance / dromajo
  RISC-V RV64GC emulator designed for RTL co-simulation
  ☆215Updated 2 months ago
• riscv-non-isa / rvv-intrinsic-doc
  ☆294Updated 3 weeks ago
• riscv-admin / riscv-ovpsim
  ☆60Updated 3 years ago
• Jonathan2251 / lbd
  ☆342Updated last month
• pulp-platform / mempool
  A 256-RISC-V-core system with low-latency access into shared L1 memory.
  ☆275Updated this week
• camel-cdr / rvv-bench
  A collection of RISC-V Vector (RVV) benchmarks to help developers write portably performant RVV code
  ☆86Updated last week
• bluespec / Piccolo
  RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
  ☆310Updated 2 years ago
• riscv / riscv-debug-spec
  Working Draft of the RISC-V Debug Specification Standard
  ☆458Updated 2 months ago
• sifive / freedom-metal
  Bare Metal Compatibility Library for the Freedom Platform
  ☆154Updated 10 months ago
• riscv / riscv-opcodes
  RISC-V Opcodes
  ☆696Updated this week
• intel / systemc-compiler
  This tool translates synthesizable SystemC code to synthesizable SystemVerilog.
  ☆248Updated 3 weeks ago
• brucehoult / rvv_example
  Simple demonstration of using the RISC-V Vector extension
  ☆36Updated 6 months ago
• csail-csg / riscy-OOO
  RiscyOO: RISC-V Out-of-Order Processor
  ☆153Updated 4 years ago